Method for forming N-shaped bottom stress liner
View Patent ↗Semiconductor devices with n-shaped bottom stress liners are formed. Embodiments include forming a protuberance on a substrate, conformally forming a sacrificial material layer over the protuberance, forming a gate stack above the sacrificial material layer on a silicon layer, removing the sacrificial material layer to form a tunnel, and forming a stress liner in the tunnel conforming to the shape of the protuberance. Embodiments further include forming a silicon layer over the sacrificial material layer and lining the tunnel with a passivation layer prior to forming the stress liner.
1. A device comprising:
a substrate having a protuberance;
a stress liner above and conforming to a shape of the protuberance; and
a gate stack above the stress liner.
2. The device according to claim 1 , further comprising:
a silicon layer above the stress liner, a surface of the silicon layer nearest the stress liner conforming to the shape of the protuberance.
3. The device according to claim 2 , wherein the gate stack is above the silicon layer.
4. The device according to claim 2 , further comprising:
source/drain regions above the silicon layer.
5. The device according to claim 2 , further comprising:
source/drain regions in the silicon layer.
6. The device according to claim 2 , further comprising:
a passivation layer between the stress liner and the silicon layer conforming to the shape of the protuberance.
7. The device according to claim 6 , comprising:
a thickness of the passivation layer being 1 to 2 nm.
8. The device according to claim 1 , further comprising:
a passivation layer between the stress liner and the substrate conforming to the shape of the protuberance.
9. The device according to claim 8 , comprising:
a thickness of the passivation layer being 1 to 2 nm.
10. The device according to claim 1 , further comprising:
a pair of shallow trench isolation (STI) structures,
wherein the protuberance is between the pair of STI structures.
11. The device according to claim 1 , wherein a thickness of the stress liner is 10 to 30 nm.
12. The device according to claim 11 , wherein the thickness of the stress liner is approximately 20 nm.
13. The device according to claim 1 , further comprising:
an additional stress liner above the gate stack.
14. The device according to claim 1 , wherein a base of the protuberance is wider than the top of the protuberance.
15. The device according to claim 1 , wherein a width of the protuberance is equal to a width of the gate stack.
16. The device according to claim 1 , wherein a width of the protuberance is greater than a width of the gate stack.
17. The device according to claim 1 , wherein a center of the gate stack and a center of the protuberance are aligned.
18. A device comprising:
a substrate having a protuberance;
a stress liner above and conforming to a shape of the protuberance; and
a gate stack above the stress liner,
wherein a center of the gate stack and a center of the protuberance are aligned, and a width of a bottom of the protuberance is greater than a width of a top of the protuberance.
19. A device comprising:
a substrate;
a pair of shallow trench isolation structures (STI) formed within or above the substrate;
a protuberance formed on a surface of the substrate and between the STI structures;
a stress liner above and conforming to a shape of the protuberance;
a silicon layer above the stress liner, a surface of the silicon layer nearest the stress liner conforming to the shape of the protuberance; and
a gate stack above the stress liner and aligned with the protuberance.
20. The device according to claim 19 , further comprising:
a first passivation layer between the stress liner and the substrate conforming to the shape of the protuberance formed to a thickness of 1 to 20 nm; and
a second passivation layer between the stress liner and the silicon layer conforming to the shape of the protuberance formed to a thickness of 1 to 20 nm,
wherein a base of the protuberance is wider than a top of the protuberance.