MOS varactors and methods for fabricating MOS varactors
A metal oxide semiconductor varactor includes an active area doped well that is disposed within a semiconductor substrate and a gate structure including a first portion that extends over the active area doped well and a second portion that extends over the semiconductor substrate outside of the active area doped well. The varactor further includes at least one active area contact structure formed in physical and electrical connection with the active area doped well, in a three-sided contact-landing area of the active area doped well. Still further, the varactor includes a gate contact structure that is formed in physical and electrical contact with the gate structure in the second portion of the gate structure such that the gate contact structure overlies the semiconductor substrate outside of the active area doped well.
1. A metal oxide semiconductor (MOS) varactor comprising:
a first active area doped well that is disposed within a semiconductor substrate and a second active area doped well that is disposed within the semiconductor substrate, the first and second active area doped wells being spaced apart from one another with respect to a surface of the semiconductor substrate;
an extended gate structure comprising a first end portion that extends over the first active area doped well, a second end portion that extends over the second active area doped well, and an intermediate portion that extends over the semiconductor substrate between the first and second active area doped wells, outside of both of the first and second active area doped wells, wherein the extended gate structure terminates proximally at a proximal end of the extended gate structure that is within the second active area doped well, wherein the extended gate structure terminates distally at a distal end of the extended gate structure that is within the first active area doped well, and wherein the extended gate structure comprises lateral sides that extend between the proximal and distal ends;
a plurality of active area contact structures formed in physical and electrical connection with the each of the first and second active area doped wells, wherein at least a first and a second contract structure of the plurality of active area contact structures are formed adjacent to opposite lateral sides of the extended gate structure at the first end portion, and at least a third contact structure of the plurality of active area contact structures is formed distally adjacent to the distal end of the extended gate structure at the first end portion; and
a gate contact structure that is formed in physical and electrical contact with the extended gate structure in the intermediate portion of the extended gate structure such that the gate contact structure overlies the semiconductor substrate between the first and second active area doped wells and outside of both of the first and second active area doped wells.
2. The MOS varactor of claim 1 , wherein at least a fourth and a fifth contact structure of the plurality of active area contact structures are formed adjacent to opposite lateral sides of the extended gate structure at the second end portion, and at least a sixth contact structure of the plurality of active area contact structures is formed proximally adjacent to the proximal end of the extended gate structure at the second end portion.
3. The MOS varactor of claim 1 , wherein the first active area doped well comprises an N-well, wherein the semiconductor substrate comprises a P-substrate, and wherein the N-well comprises a plurality of heavily-doped N-type areas, the active area contacts being formed to the heavily-doped N-type areas.
4. The MOS varactor of claim 3 , wherein the first through third contact structures of the plurality of active area contact structures are formed within a first three-sided contact-landing area that surrounds the first end portion of the extended gate structure, and wherein the fourth through sixth contact structure of the plurality of active area contact structures are formed within a second three-sided contact-landing area that surrounds the second end portion of the extended gate structure.
5. The MOS varactor of claim 4 , further comprising a further gate structure formed partially over the first active area doped well partially over the semiconductor substrate outside of the first active area doped well, and partially over the second active area doped well.
6. The MOS varactor of claim 5 , further comprising a further gate contact structure formed over the further gate structure and over the semiconductor substrate outside of the first and second active area doped wells.