High-K metal gate device
View Patent ↗A method of forming a semiconductor device is presented. The method includes providing a substrate. The method further includes forming a gate stack having a gate electrode on the substrate, which includes forming a metal gate electrode layer. A buffer gate electrode layer is formed on top of the metal gate electrode layer and a top gate electrode layer having a poly-silicon alloy is formed over the metal gate electrode layer.
1. A method of forming a semiconductor device comprising:
providing a substrate; and
forming a gate stack having a gate electrode over a composite gate dielectric layer having more than two different dielectric layers on the substrate, comprising
forming a metal gate electrode layer over the composite gate dielectric layer, and
forming a top gate electrode layer directly over and contacts the metal gate electrode layer, wherein the top gate electrode layer comprises poly-silicon alloy, the top gate electrode layer being the uppermost gate electrode layer of the gate stack and the top gate electrode layer reduces resistance between the metal gate electrode layer and the top gate electrode layer.
2. The method of claim 1 wherein:
the poly-silicon alloy includes poly-silicon germanium (SiGe) and has a thickness of about 100-800 Å.
3. The method of claim 2 wherein the SiGe layer includes Ge content of about 1-60 mole fraction.
4. The method of claim 1 wherein the metal gate electrode layer includes TiN, TaN, TiAlN, TaN/TiN, TaC or TaCN.
5. The method of claim 1 wherein the composite gate dielectric layer comprises first, second and third dielectric layers.
6. The method of claim 5 wherein the second dielectric layer includes a high-K dielectric material which is provided on top of the first dielectric layer.
7. A method of forming a semiconductor device comprising:
providing a substrate; and
forming a gate stack having a gate electrode over a composite gate dielectric layer having more than two different dielectric layers on the substrate, comprising
forming a metal gate electrode layer over the composite gate dielectric layer, and
forming a top gate electrode layer directly over and contacts the metal gate electrode layer, the top gate electrode layer being the uppermost layer, the top gate electrode layer reduces resistance between the metal gate electrode layer and the top gate electrode layer of the gate stack.
8. The method of claim 7 wherein the top gate electrode layer comprises a poly-silicon alloy which includes poly-silicon germanium (SiGe).
9. The method of claim 8 wherein the SiGe layer includes Ge content of about 1-60 mole fraction.
10. The method of claim 7 wherein the metal gate electrode layer includes TiN, TaN, TiAlN, TaN/TiN, TaC or TaCN and has a thickness of about 50-200 Å.
11. The method of claim 7 wherein the composite gate dielectric layer comprises first, second and third dielectric layers.
12. The method of claim 11 wherein the second dielectric layer includes a high-K dielectric material which is provided on top of the first dielectric layer.
13. The method of claim 12 wherein the high-K dielectric material includes Hf-based high-K, Al-based high-K, Zr-based high-K or a combination thereof.
14. The method of claim 7 wherein the top gate electrode layer comprises a poly-silicon alloy which is doped with p-type dopants.
15. The method of claim 14 wherein the poly-silicon alloy comprises poly-silicon germanium.
16. The method of claim 15 wherein the p-type dopants comprise boron.