Transistor with source-drain silicide pullback

1. A method of forming a device, comprising:

providing a substrate, wherein the substrate is prepared with

a low voltage (LV) device region, and

a medium voltage (MV) device region;

forming a LV gate in the LV device region;

forming LV lightly doped (LD) regions in the substrate in the LV device region adjacent to the LV gate;

forming a MV gate in the MV device region;

forming MV lightly doped (LD) regions in the substrate in the MV device region adjacent to the MV gate;

forming a spacer layer on the substrate, wherein the spacer layer lines the substrate, the LV gate and the MV gate;

patterning the spacer layer, wherein patterning the spacer layer simultaneously forms first and second non-extended spacers on first and second sidewalls of the LV gate, and a first extended L-shaped spacer on a first sidewall of the MV gate, wherein the first extended L-shaped spacer overlaps a top surface of the MV gate by an overlapping portion, and a portion of the top surface of the MV gate adjacent to the overlapping portion is exposed;

forming LV heavily doped (HD) regions in the substrate adjacent to the non-extended spacers on first and second sidewalls of the LV gate; and

forming first and second MV heavily doped (HD) regions in the substrate, wherein the first MV HD region is adjacent to the first extended L-shaped spacer on the first sidewall of the MV gate, wherein the first extended L-shaped spacer displaces the first MV HD region from the first sidewall of the MV gate by a MV distance D M which is sufficient to reduce gate induced drain leakage (GIDL) and impact ionization of a MV transistor in the MV device region.

2. The method of claim 1 wherein the non-extended spacers and the first extended L-shaped spacer are composite spacers, and the composite spacers comprise a silicon oxide layer and a silicon nitride layer.

3. The method of claim 1 further comprising:

forming metal silicide contacts on the LV HD regions, the first and second MV HD regions, a top surface of the LV gate, and the exposed portion of the top surface of the MV gate.

4. The method of claim 3 wherein the metal silicide contacts comprise nickel-based silicide or cobalt silicide.

5. The method of claim 1 wherein the MV LD regions have lighter dopant concentrations than the LV LD regions.

6. The method of claim 1 wherein the LV LD region is formed by an angle implant.

7. The method of claim 1 wherein the MV LD region is formed either by an angle implant or by having a specific implant opening extended into a gate edge before the MV gate formation.

8. The method of claim 1 wherein:

the first sidewall of the MV gate with the first extended-shaped L spacer is a drain side having high drain bias; and

a second sidewall of the MV gate comprises a non-extended MV spacer to form an asymmetrical MV transistor.

9. The method of claim 1 wherein patterning the spacer layer forms:

the first extended L-shaped spacer on the first sidewall of the MV gate, and

a second extended L-shaped spacer on a second sidewall of the MV gate; and

wherein the top surface of the MV gate between the first and second extended L-shaped spacers is exposed, and the first and second extended L-shaped spacers displace the first and second MV HD regions by the distance D M which is sufficient to reduce the GIDL and impact ionization of the MV transistor.

10. The method of claim 1 wherein the overlapping portion has a length O G equal to about 10 nm.

11. A method of forming a device, comprising:

providing a substrate, wherein the substrate is prepared with

a low voltage (LV) device region, and

a medium voltage (MV) device region;

forming a LV gate in the LV device region;

forming LV lightly doped (LD) regions in the substrate in the LV device region adjacent to the LV gate;

forming a MV gate in the MV device region;

forming MV lightly doped (LD) regions in the substrate in the MV device region adjacent to the MV gate;

forming a spacer layer on the substrate, the spacer layer lines the substrate, the LV gate and the MV gate;

patterning the spacer layer, wherein patterning the spacer layer simultaneously forms first and second non-extended spacers on first and second sidewalls of the LV gate, and a first extended L-shaped spacer on a first sidewall of the MV gate, wherein a portion of a top surface of the MV gate adjacent to the first extended L-shaped spacer is exposed;

forming LV heavily doped (HD) regions in the substrate adjacent to the non-extended spacers on first and second sidewalls of the LV gate; and

forming first and second MV heavily doped (HD) regions in the substrate, wherein the first MV HD region is adjacent to the first extended L-shaped spacer on the first sidewall of the MV gate, wherein the first extended L-shaped spacer displaces the first MV HD region from the first sidewall of the MV gate by a MV distance D M which is sufficient to reduce gate induced drain leakage (GIDL) and impact ionization of a MV transistor in the MV device region,

wherein patterning the spacer layer comprises:

forming a mask layer on the substrate covering the spacer layer,

patterning the mask layer to form a patterned etch mask which protects the spacer layer where the extended L-shaped spacers are to be formed and exposes remaining portions of the spacer layer,

performing an anisotropic etch using the patterned etch mask to form the non-extended spacers on first and second sidewalls of the LV gate and the first extended L-shaped spacer the first sidewall of the MV gate, and

removing the patterned etch mask by ashing.

12. A method of forming a device, comprising:

providing a substrate, wherein the substrate is includes a medium voltage (MV) device region;

forming a MV gate in the MV device region;

forming MV lightly doped (LD) regions in the substrate in the MV device region adjacent to the MV gate;

forming a spacer layer on the substrate, the spacer layer lines the substrate and the MV gate;

patterning the spacer layer, wherein patterning the spacer layer forms a first extended L-shaped spacer on a first sidewall of the MV gate and a second extended L-shaped spacer on a second sidewall of the MV gate, wherein the first extended L-shaped spacer includes an overlapping portion that extends across a top surface of the MV gate by a length, O G , and a portion of a top surface of the MV gate adjacent the overlapping portion and between the first extended L-shaped spacer and the second extended L-shaped spacer is exposed; and

forming first and second MV heavily doped (HD) regions in the substrate, wherein the first MV HD region is adjacent to the first extended L-shaped spacer, wherein the first extended L-shaped spacer displaces the first MV HD region from the first sidewall of the MV gate by a MV distance D M , and the second extended L-shaped spacer displaces the second MV HD region from the second sidewall of the MV gate by the MV distance D M .

13. The method of claim 12 wherein the MV distance D M is sufficient to reduce GIDL and impact ionization of a MV transistor in the MV device region.

14. The method of claim 12 wherein the first extended L-shaped spacer is a composite spacer, and the composite spacer comprises a silicon oxide layer and a silicon nitride layer.

15. The method of claim 12 further comprising:

providing metal silicide contacts on the first and second MV HD regions and on the exposed top surface of the MV gate.

16. The method of claim 15 wherein the metal silicide contacts comprise nickel-based silicide or cobalt silicide.

17. The method of claim 12 wherein the substrate further includes a low voltage (LV) device region, and further comprising:

forming a LV gate in the LV device region;

forming LV lightly doped (LD) regions in the substrate in the LV device region adjacent to the LV gate;

wherein patterning the spacer layer also forms first and second non-extended spacers on first and second sidewalls of the LV gate; and

forming LV HD regions in the substrate adjacent to the non-extended spacers on the first and second sidewalls of the LV gate.

18. The method of claim 12 wherein the length O G is equal to about 10 nm.