MOS varactors with large tuning range

1. A device comprising:

a substrate with a first well of a first polarity type, wherein the first well defines a varactor region, the first well comprising a lower first well boundary located above a bottom surface of the substrate;

a second well in the varactor region, the second well comprises a buried well of a second polarity type having an upper second well boundary disposed below an upper portion of the first well from an upper first well boundary to the upper second well boundary and a lower second well boundary disposed above the lower first well boundary, wherein an interface of the second well and the upper portion of the first well forms a shallow PN junction in the varactor region; and

a gate structure in the varactor region, the upper portion of the first well beneath the gate structure forms a channel region of the device, wherein in depletion mode, a depletion region under the gate structure in the channel region merges with a depletion region of the shallow PN junction.

2. The device of claim 1 wherein:

the first polarity type comprises n-type, the second polarity type comprises p-type, and the device comprises an n-MOS varactor; or

the first polarity type comprises p-type, the second polarity type comprises n-type, and the device comprises a p-MOS varactor.

3. The device of claim 1 comprises contact regions that include heavily doped regions of the first polarity type in the substrate, wherein the contact regions are adjacent to first and second opposite sides of the gate structure.

4. The device of claim 3 wherein the contact regions are electrically coupled to the upper portion of the first well above the second well.

5. The device of claim 3 comprises a bias terminal coupled to the contact regions, wherein a bias voltage is applied to the bias terminal.

6. The device of claim 1 wherein the gate structure comprises a gate dielectric below a gate electrode.

7. The device of claim 6 comprises sidewall spacers on first and second opposite sidewalls of the gate structure.

8. The device of claim 7 wherein:

the first polarity type comprises n-type, the second polarity type comprises p-type, and the device comprises an n-MOS varactor; or

the first polarity type comprises p-type, the second polarity type comprises n-type, and the device comprises a p-MOS varactor.

9. The device of claim 6 comprises an input terminal coupled to the gate electrode, wherein the input terminal is coupled to an input voltage comprising a range from depletion to accumulation input voltages.

10. An integrated circuit (IC) comprising:

a substrate prepared with a first well, the first well defining a varactor region, the first well comprises a first polarity type, the first well comprising a lower first well boundary located above a bottom surface of the substrate;

a second well in the varactor region, the second well comprises a buried well of a second polarity type having an upper second well boundary disposed below an upper portion of the first well from an upper first well boundary to the upper second well boundary and a lower second well boundary disposed above the lower first well boundary, wherein an interface of the second well and the upper portion of the first well forms a shallow PN junction in the varactor region; and

a gate structure in the varactor region, the upper portion of the first well beneath the gate structure forms a channel region of the varactor, wherein in depletion mode, a depletion region under the gate structure in the channel region merges with a depletion region of the shallow PN junction.

11. The IC of claim 10 wherein:

the first polarity type comprises n-type, the second polarity type comprises p-type, and the varactor comprises an n-MOS varactor; or

the first polarity type comprises p-type, the second polarity type comprises n-type, and the varactor comprises a p-type MOS varactor.

12. The IC of claim 10 wherein the gate structure comprises a gate dielectric below a gate electrode.

13. The IC of claim 12 comprises of contact regions that include heavily doped regions of the first polarity type in the substrate, wherein the contact regions are adjacent to first and second opposite sidewalls of the gate structure.

14. The IC of claim 13 comprises an input terminal coupled to the gate electrode, wherein the input terminal is coupled to an input voltage comprising a range from depletion to accumulation input voltages.

15. The IC of claim 12 comprises an input terminal coupled to the contact regions, wherein the input terminal is coupled to an input voltage comprising a range from depletion to accumulation input voltages.

16. The IC of claim 10 comprises of contact regions that include heavily doped regions of the first polarity type in the substrate, wherein the contact regions are adjacent to first and second opposite sidewalls of the gate structure.

17. The IC of claim 16 wherein the channel is electrically coupled to the contact regions.

18. An apparatus comprising:

a substrate with a first well, the first well defining a varactor region, the first well comprises a first polarity type, the first well comprising a lower first well boundary located above a bottom surface of the substrate;

a second well in the varactor region, the second well comprises a buried well of a second polarity type having an upper second well boundary disposed below an upper portion of the first well from an upper first well boundary to the upper second well boundary and a lower second well boundary disposed above the lower first well boundary, wherein an interface of the second well and the upper portion of the first well forms a shallow PN junction in the varactor region; and

a gate structure and contact regions in the varactor region, the contact regions are adjacent to first and second opposite sidewalls of the gate structure, the upper portion of the first well beneath the gate structure forms a channel region of the apparatus, wherein in depletion mode, a depletion region under the gate structure in the channel region merges with a depletion region of the shallow PN junction.

19. The apparatus of claim 18 wherein the contact regions include heavily doped regions of the first polarity type in the substrate.

20. The apparatus of claim 19 wherein the channel is electrically coupled to the contact regions.