Integrated circuits with gaps
View Patent ↗Integrated circuits and methods of producing such integrated circuits are provided. In one example, an integrated circuit has a working layer that includes a semiconductor substrate. A handle layer underlies the working layer, where a gap is defined in the handle layer such that an upper gap surface underlies the working layer. The gap has a gap area measured along a first plane at the gap upper surface. A switch directly overlies the gap, where the switch has a switch area measured along a second plane parallel with the first plane. The switch area is less than the gap area.
1. An integrated circuit comprising:
a working layer comprising a semiconductor substrate;
a buried oxide layer underlying the working layer;
a handle layer underlying the buried oxide layer, wherein the handle layer defines a gap underlying the buried oxide layer, wherein the gap comprises an upper gap surface and a lower gap surface, and wherein the handle layer comprises a handle semiconductor layer and a handle insulator layer; and
a switch overlying the buried oxide layer, wherein the switch comprises a source, a drain, and a gate, and wherein the entire switch directly overlies the gap.
2. The integrated circuit of claim 1 wherein the gap comprises gap side surfaces formed from the handle layer, and wherein the lower gap surface is formed from the handle layer.
3. The integrated circuit of claim 1 wherein the switch comprises a field effect transistor.
4. The integrated circuit of claim 3 wherein the field effect transistor comprises the source and the drain, wherein the source extends completely through the working layer and the drain extends completely through the working layer.
5. The integrated circuit of claim 1 wherein the switch comprises a plurality of switches directly overlying one gap.
6. The integrated circuit of claim 5 wherein an entirety of the plurality of switches directly overlie one gap.
7. The integrated circuit of claim 1 wherein the handle insulator layer underlies the gap.
8. The integrated circuit of claim 7 wherein the handle semiconductor layer defines gap side surfaces and the handle insulator layer defines a gap bottom surface.
9. The integrated circuit of claim 1 further comprising a gap gas positioned within the gap, wherein the gap gas comprises air.