RRAM structure at STI with Si-based selector
View Patent ↗An RRAM at an STI region is disclosed with a vertical BJT selector. Embodiments include defining an STI region in a substrate, implanting dopants in the substrate to form a well of a first polarity around and below an STI region bottom portion, a band of a second polarity over the well on opposite sides of the STI region, and an active area of the first polarity over each band of second polarity at the surface of the substrate, forming a hardmask on the active areas, removing an STI region top portion to form a cavity, forming an RRAM liner on cavity side and bottom surfaces, forming a top electrode in the cavity, removing a portion of the hardmask to form spacers on opposite sides of the cavity, and implanting a dopant of the second polarity in a portion of each active area remote from the cavity.
1. A method comprising: defining a shallow trench isolation (STI) region in a substrate; implanting dopants in the substrate to form a well of a first polarity around and below a bottom portion of the STI region, a band of a second polarity over the well on opposite sides of the STI region, and active areas of the first polarity over the band of the second polarity on the opposite sides of the STI region at—a top surface of the substrate; forming a hardmask on the active areas; removing a top portion of the STI region to form a cavity; forming a resistive random access memory (an RRAM) liner on side and bottom surfaces of the cavity; forming a top electrode in the cavity; removing a portion of the hardmask to form spacers on opposite sides of the cavity; and implanting one or more dopants of the second polarity in a portion of each active area remote from the cavity.
2. The method according to claim 1 , wherein the bottom surface of the cavity is above a top surface of the band of a second polarity.
3. The method according to claim 1 , comprising forming each of the active areas with a shallow implant and implanting—dopants of the second polarity in each active area using multiple energies.
4. The method according to claim 3 , comprising activating all of the dopants after implanting the dopants of the second polarity in each active area.
5. The method according to claim 4 , comprising forming the hardmask of silicon nitride.
6. The method according to claim 1 , comprising forming the RRAM liner to a thickness of 3 nanometers (nm) to 900 nm.
7. The method according to claim 1 , wherein the RRAM liner comprises an oxide of a transition metal.
8. The method according to claim 1 , wherein the top electrode comprises a transition metal, titanium nitride (TiN), TiN/Ti, or polysilicon.
9. A method comprising: defining a shallow trench isolation (STI) region in a substrate; implanting dopants in the substrate to form a well of a first polarity around and below a bottom portion of the STI region, a band of a second polarity over the well on opposite sides of the STI region, and active areas of the first polarity over the band of the second polarity on the opposite sides of the STI region at a top surface of the substrate; forming a hardmask on the active areas; removing a top portion of the STI region to form a cavity; forming a sacrificial top electrode in the cavity; removing a portion of the hardmask to form spacers on opposite sides of the cavity; implanting one or more dopants of the second polarity in a portion of each active area remote from the cavity; removing the sacrificial top electrode; forming a resistive random access memory (an RRAM) liner on side and bottom surfaces of the cavity; and forming a top electrode in the cavity.
10. The method according to claim 9 , wherein the bottom surface of the cavity is above a top surface of the band of a second polarity.
11. The method according to claim 9 , comprising forming each of the active areas with a shallow implant and implanting dopants of the second polarity in each active area using multiple energies.
12. The method according to claim 9 , comprising activating all of the dopants prior to removing the sacrificial top electrode.
13. The method according to claim 12 , comprising forming a protection layer over the active areas prior to removing the sacrificial top electrode.
14. The method according to claim 9 , comprising forming the hardmask of silicon nitride.
15. The method according to claim 9 , comprising forming the RRAM liner of an oxide of a transition metal and to a thickness of 3 nanometers (nm) to 900 nm.
16. The method according to claim 9 , wherein the top electrode comprises a transition metal, titanium nitride (TiN), TiN/Ti, or polysilicon.