Integration of eNVM, RMG, and HKMG modules
View Patent ↗A memory device is fabricated through the integration of embedded non-volatile memory (eNVM) with replacement metal gate (RMG) and high-k/metal gate (HKMG) modules. Embodiments include forming two substrate portions having upper surfaces at different heights, forming non-volatile gate stacks over the substrate portion with the lower upper surface, and forming high-voltage gate stacks and logic gate stacks over the other substrate portion. Embodiments include the upper surfaces of the non-voltage gate stacks, the high-voltage gate stacks, and the logic gate stacks being substantially coplanar.
1. A method comprising:
forming first and second substrate portions in a substrate, the first substrate portion having a first upper surface and the second substrate portion having a second upper surface, wherein the first upper surface is higher than the second upper surface by a step height;
forming a high-voltage gate stack having a third upper surface and a logic gate stack having a fourth upper surface, both over the first substrate portion; and
forming a non-volatile gate stack having a fifth upper surface over the second substrate portion,
wherein the third, fourth, and fifth upper surfaces are substantially coplanar.
2. The method according to claim 1 , comprising:
forming the non-volatile gate stack with an oxide-nitride-oxide (ONO) stack between two polysilicon layers; and
forming the step height to be substantially equal to a combined height of the ONO stack and one of the polysilicon layers.
3. The method according to claim 1 , comprising forming the step height to 1000 Å to 1500 Å.
4. The method according to claim 1 , comprising forming a shallow trench isolation (STI) region between the first substrate portion and the second substrate portion.
5. The method according to claim 4 , comprising extending the STI region 2000 Å to 8000 Å below the first upper surface.
6. The method according to claim 4 , comprising:
forming a first portion in the STI region adjacent the first substrate portion and having a first STI upper surface higher than the first upper surface by a second step height; and
forming a second portion in the STI region adjacent the second substrate portion and having a second STI upper surface higher than the second upper surface by a third step height.
7. The method according to claim 6 , wherein the second step height and the third step height are substantially the same.
8. The method according to claim 1 , wherein the high-voltage gate stack is a replacement metal gate (RMG) stack and the logic gate stack is a high-k/metal gate (HKMG) stack.
9. A device comprising:
a substrate with a first substrate portion having a first upper surface and a second substrate portion having a second upper surface, wherein the first upper surface is higher than the second upper surface by a step height;
a high-voltage gate stack having a third upper surface and a logic gate stack having a fourth upper surface, both over the first substrate portion; and
a non-volatile gate stack having a fifth upper surface over the second substrate portion,
wherein the third, fourth, and fifth upper surfaces are substantially coplanar.
10. The device according to claim 9 , wherein the non-volatile gate stack includes an oxide-nitride-oxide (ONO) stack between two polysilicon layers, and the step height is substantially equal to a combined height of the ONO stack and one of the polysilicon layers.
11. The device according to claim 9 , wherein the step height is 1000 Å to 1500 Å.
12. The device according to claim 9 , further comprising a shallow trench isolation (STI) region between the first substrate portion and the second substrate portion.
13. The device according to claim 12 , wherein the STI region extends 2000 Å to 8000 Å below the first upper surface.
14. The device according to claim 12 , wherein:
the STI region comprises a first STI portion having a first STI upper surface and a second STI portion having a second STI upper surface;
the first STI upper surface is higher than the first upper surface by a second step height; and
the second STI upper surface is higher than the second upper surface by a third step height.
15. The device according to claim 14 , wherein the second step height and the third step height are substantially the same.
16. The device according to claim 9 , wherein the high-voltage gate stack is a replacement metal gate (RMG) stack and the logic gate stack is a high-k/metal gate (HKMG) stack.
17. A method comprising:
providing a substrate having a first portion and a second portion, the first portion having a first upper surface;
etching the second portion of the substrate to form a second upper surface, the first upper surface being higher than the second upper surface by a step height;
forming a high-voltage gate stack having a third upper surface and a logic gate stack having a fourth upper surface, both over the first portion;
forming a non-volatile gate stack having a fifth upper surface over the second portion, the non-volatile gate stack including an oxide-nitride-oxide (ONO) stack between two polysilicon layers, wherein the step height is substantially equivalent to a combined height of the ONO stack and one of the polysilicon layers; and
planarizing the third, fourth, and fifth upper surfaces to be substantially coplanar.
18. The method according to claim 17 , comprising:
forming a shallow trench isolation (STI) region between the first substrate portion and the second substrate portion and extending 2000 Å to 8000 Å below the first upper surface; and
deglazing the STI region to form a first STI upper surface of a first portion of the STI region higher than the first upper surface by a second step height and a second STI upper surface of a second portion of the STI region higher than the second upper surface by the second step height.