Determination of lithography tool process condition

1. A method for forming an integrated circuit (IC) comprising:

providing a wafer having a substrate prepared with a photoresist layer;

processing the photoresist layer by passing a radiation from an exposure source of a lithography tool through a mask having a pattern, wherein process parameters of the lithography tool which is used to process the photoresist layer is determined by performing a pattern matching process; and

developing the photoresist layer to transfer the pattern on the mask to the photoresist layer.

2. The method of claim 1 wherein the pattern matching process comprises:

providing a baseline lithography plot;

selecting a model which describes the baseline lithography plot;

forming a list of reference plots;

providing inline lithography plot;

comparing the inline lithography plot with the list of reference plots; and

selecting a reference plot from the list of reference plots which best matches the inline lithography plot.

3. The method of claim 2 wherein providing the baseline lithography plot comprises:

collecting baseline lithography data from a baseline wafer; and

presenting the baseline lithography data in a Bossung plot, wherein the Bossung plot serves as the baseline lithography plot.

4. The method of claim 3 wherein the baseline wafer comprises a golden wafer.

5. The method of claim 4 wherein the baseline lithography data relates to one or more process parameters of a lithography tool which operates at an optimum condition.

6. The method of claim 5 wherein the selected model is described using an equation which correlates a feature parameter as a function of the one or more process parameters of the lithography tool which operates at the optimum condition.

7. The method of claim 6 wherein the feature parameter comprises critical dimension (CD), sidewall angle or height of a feature formed on the golden wafer and the one or more process parameters comprise stepper focus or exposure settings of the lithography tool which operates at the optimum condition.

8. The method of claim 6 wherein the selected model is presented in the form of CD=MackCDmodel(E,F).

9. The method of claim 2 wherein forming the list of reference plots comprises:

forming a reference model based on the selected model; and

creating one or more reference Bossung plots by providing one or more sets of offset values to the reference model, wherein the one or more reference Bossung plots serve as the list of reference plots.

10. The method of claim 9 wherein the reference model is presented in the form of CD=MackCDmodel(E+ΔE, F+ΔF).

11. The method of claim 2 wherein providing inline lithography plot comprises:

collecting inline lithography data; and

presenting the inline lithography data in a Bossung plot, wherein the Bossung plot serves as the inline lithography plot.

12. The method of claim 11 wherein the inline lithography data is collected from the wafer.

13. The method of claim 12 wherein the inline lithography data relates to one or more process parameters of the lithography tool used to process the photoresist layer.

14. The method of claim 2 further comprising:

extracting offset values from the reference plot which best matches the inline lithography plot; and

adding the extracted offset values to baseline lithography data to determine the process parameters of the lithography tool used to process the photoresist layer.

15. A method for determining process parameters of a lithography tool used for processing a wafer comprising:

performing a pattern matching process using a plurality of patterns, wherein the patterns comprise a plurality of lithography plots which are presented to show the relationship of a feature parameter as a function of one or more process parameters of a lithography tool to determine the process parameters of the lithography tool used for processing the wafer.

16. The method of claim 15 wherein performing the pattern matching process comprises:

providing a baseline lithography plot;

selecting a model which describes the baseline lithography plot;

forming a list of reference plots;

providing inline lithography plot;

comparing the inline lithography plot with the list of reference plots; and

selecting a reference plot from the list of reference plots which best matches the inline lithography plot.

17. The method of claim 16 wherein providing the baseline lithography plot comprises:

collecting baseline lithography data from a baseline wafer; and

presenting the baseline lithography data in a Bossung plot, wherein the Bossung plot serves as the baseline lithography plot.

18. The method of claim 17 wherein the baseline wafer comprises a golden wafer.

19. The method of claim 18 wherein the baseline lithography data relates to one or more process parameters of a lithography tool which operates at an optimum condition.

20. The method of claim 19 wherein the selected model is described using an equation which correlates a feature parameter as a function of the one or more process parameters of the lithography tool which operates at the optimum condition.

21. A method for forming an integrated circuit (IC) comprising:

providing a wafer having a substrate prepared with a photoresist layer;

processing the photoresist layer by passing a radiation from an exposure source of a lithography tool through a mask having a pattern, wherein process parameters of the lithography tool is determined by performing a pattern matching process, and wherein the pattern matching process comprises

providing a baseline lithography plot;

selecting a model which describes the baseline lithography plot;

forming a list of reference plots;

providing inline lithography plot;

comparing the inline lithography plot with the list of reference plots; and

selecting a reference plot from the list of reference plots which best matches the inline lithography plot; and

developing the photoresist layer to transfer the pattern on the mask to the photoresist layer.