Integrated circuit structures with spin torque transfer magnetic random access memory having increased memory cell density and methods for fabricating the same

1. An integrated circuit comprising:

a word line layer;

a bit line layer;

a magnetic random access memory (MRAM) stack in contact with the bit line layer;

a first doped silicon layer in contact with the MRAM stack, the first doped silicon layer comprising conductivity-determining ions of a first type;

a second doped silicon layer in contact with the first doped silicon layer and further in contact with the word line layer, the second doped silicon layer comprising conductivity-determining ions of a second type that is opposite the first type;

a third doped silicon layer in contact with the second doped silicon layer; and

a source line layer in electrical contact with the third doped silicon layer,

wherein the word line layer extends substantially perpendicularly with respect to the bit line layer, the integrated circuit further comprising a first interlayer dielectric (ILD) layer below the first doped silicon layer and a second ILD layer above the first doped silicon layer, wherein the first doped silicon layer and the first and second ILD layer form a common sidewall that extends vertically above the word line layer, and wherein the second doped silicon layer is formed along the common sidewall along the first doped silicon layer and the first and second ILD layers.

2. The integrated circuit of claim 1 , wherein the third doped silicon layer comprises conductivity ions of the first type.

3. The integrated circuit of claim 2 , wherein each of the word line layer, bit line layer, and source line layers comprise a metal material.

4. The integrated circuit of claim 1 , wherein the source line layer is in electrical contact with the third doped silicon layer which in turn is in contact with the second doped silicon layer, the third doped silicon layer comprising conductivity ions of the first type.

5. The integrated circuit of claim 4 , wherein the word line layer and the bit line layers comprise a metal material.

6. The integrated circuit of claim 1 , wherein the MRAM stack comprises a top electrode, a magnetic tunnel junction (MTJ) stack, and a bottom electrode, or, alternatively, wherein the MRAM stack is replaced with an RRAM, PCRAM, or any other memory element.

7. The integrated circuit of claim 6 , wherein the MTJ stack comprises a fixed layer, a free layer, and a barrier layer between the fixed layer and the free layer.

8. The integrated circuit of claim 1 , wherein the first doped silicon layer comprises a plurality of discontinuous segments, each such segment being in contact with one MRAM stack.

9. The integrated circuit of claim 1 , wherein the source line layer extends parallel to the common sidewall and is separated from the common sidewall by the third doped silicon layer.

10. The integrated circuit of claim 1 , wherein the first conductivity-determining ion type is n-type and the second conductivity-determining ion type is p-type.

11. A method for fabricating an integrated circuit comprising:

forming a word line layer;

forming a bit line layer, wherein the word line layer is formed so as to extend substantially perpendicularly with respect to the bit line layer;

forming a magnetic random access memory (MRAM) stack in contact with the bit line layer;

forming a spacer structure surrounding the MRAM stack;

forming a first doped silicon layer in contact with the MRAM stack, the first doped silicon layer comprising conductivity-determining ions of a first type;

forming a trench through the first doped silicon layer to expose an end portion of the first doped silicon layer;

forming a second doped silicon layer in contact with the end portion of the first doped silicon layer and further in contact with the word line layer, the second doped silicon layer comprising conductivity-determining ions of a second type that is opposite the first type;

forming a third doped silicon layer in contact with the second doped silicon layer;

forming a source line layer in electrical contact with the third doped silicon layer; and

forming a first interlayer dielectric (ILD) layer below the first doped silicon layer and a second ILD layer above the first doped silicon layer, wherein forming the trench comprises forming a trench through the first and second ILD layers in addition to through the first doped silicon layer, wherein forming the second doped silicon layer comprises forming a second doped silicon layer along the first and second ILD layers within the trench, and wherein the first doped silicon layer and the first and second ILD layer are formed so as to form a common sidewall that extends vertically above the word line layer, and wherein the second doped silicon layer is formed along the common sidewall along the first doped silicon layer and the first and second ILD layers.

12. The method of claim 11 , wherein forming the first doped silicon layer comprises forming an n-type doped silicon layer, and wherein forming the second doped silicon layer comprises forming a p-type doped silicon layer.