ESD protection circuit
View Patent ↗A device having a substrate defined with a device region is presented. The device region includes an ESD protection circuit having a transistor. The transistor includes a gate having first and second sides, a first diffusion region adjacent to the first side of the gate and a second diffusion region displaced away from the second side of the gate. The device includes a first device well which encompasses the device region and a second device well disposed within the first device well. The device further includes a drift well which encompasses the second diffusion region of which edges of the drift well do not extend below the gate and is away from a channel region, and a drain well which is disposed under the second diffusion region and extends below the gate.
1. A device comprising:
a substrate defined with a device region, the device region comprises an ESD protection circuit having a transistor, wherein the transistor includes
a gate having first and second sides,
a first diffusion region adjacent to the first side of the gate, and
a second diffusion region displaced away from the second side of the gate, wherein the first and second diffusion regions comprise dopants of a first polarity type;
a first device well encompasses the device region and a second device well disposed within the first device well;
a drift well which encompasses the second diffusion region, wherein edges of the drift well do not extend below the gate and is away from a channel region; and
a drain well having dopants of the first polarity type encompasses the second diffusion region and extends below the gate.
2. The device of claim 1 wherein the first device well comprises dopants of the first polarity type and the second device well comprises dopants of a second polarity type.
3. The device of claim 2 wherein the first polarity type comprises n type and the second polarity type comprises p type.
4. The device of claim 1 wherein the second device well encompasses at least the first diffusion region and a part of the gate.
5. The device of claim 4 wherein the second device well encompasses the gate and the first and second diffusion regions.
6. The device of claim 1 wherein the first device well and the drift well comprise dopants of the first polarity type and the second device well comprises dopants of a second polarity type.
7. The device of claim 6 wherein the first polarity type comprises n type and the second polarity type comprises p type.
8. The device of claim 1 wherein the drift well is narrower than the drain well.
9. The device of claim 1 wherein a first edge of the drift well is below a bottom of a device isolation region adjacent to the second diffusion region and a second edge of the drift well extends beyond the second diffusion region.
10. The device of claim 1 wherein the drain well is shallower than the drift well.
11. The device of claim 1 wherein the drain well comprises a width which is larger than a width of the second diffusion region.
12. A device comprising:
a substrate defined with a device region, the device region comprises an ESD protection circuit having a transistor, wherein the transistor includes
a gate having first and second sides,
a first diffusion region adjacent to the first side of the gate, and
a second diffusion region displaced away from the second side of the gate;
a first device well encompasses the device region and a second device well disposed within the first device well;
a drift well which encompasses the second diffusion region, wherein edges of the drift well do not extend below the gate and is away from a channel region; and
a drain well disposed under the second diffusion region and extends beyond the drift well.
13. The device of claim 12 wherein:
the first device well comprises dopants of the first polarity type and the second device well comprises dopants of a second polarity type; and
the first and second diffusion regions comprise dopants of a first polarity type.
14. The device of claim 13 wherein the first polarity type comprises n type and the second polarity type comprises p type.
15. The device of claim 12 wherein a first edge of the drift well is below a bottom of a device isolation region adjacent to the second diffusion region and a second edge of the drift well extends beyond the second diffusion region.
16. The device of claim 12 wherein the drain well underlaps a portion of the gate.
17. The device of claim 12 wherein the transistor is devoid of a drift isolation region disposed between the gate and the second diffusion region.
18. The device of claim 12 wherein the drift well is narrower than the drain well.
19. The device of claim 12 wherein the drain well is shallower than the drift well.
20. The device of claim 12 wherein the drain well comprises a width which is larger than a width of the second diffusion region.