Integrated circuits with alignment marks and methods of producing the same
View Patent ↗Methods of producing integrated circuits with interposers and integrated circuits produced from such methods are provided. In an exemplary embodiment, a method of producing an integrated circuit includes forming a base layer overlying a substrate, and forming an alignment mark overlying the base layer. A first layer is formed overlying the base layer and the alignment mark, and the first layer has a first layer thickness. A second layer is formed overlying the first layer, where the second layer has a second layer thickness and where a combined thickness of the first and second layer thicknesses is from about 2 to about 50 micrometers. A second component is formed from the second layer.
1. A method of producing an integrated circuit comprising:
forming a base layer overlying a substrate;
forming an alignment mark overlying the base layer;
forming a first layer overlying the base layer and the alignment mark, wherein the first layer comprises a first layer thickness;
forming a second layer overlying the first layer, wherein the second layer comprises a second layer thickness, and wherein a combined thickness of the first layer thickness and the second layer thickness is from about 2 micrometers to about 50 micrometers; and
forming a second component from the second layer, wherein forming the second component comprises viewing the alignment mark through the first layer and the second layer, wherein the first layer comprises a first refractive index measured at 589 nanometers, wherein the second layer comprises a second refractive index measured at 589 nanometers, and wherein the second refractive index is within about 0.05 units of the first refractive index.
2. The method of claim 1 wherein forming the second component comprises forming the second component wherein the second refractive index is within about 0.02 units of the first refractive index.
3. The method of claim 1 wherein:
forming the first layer comprises forming the first layer comprising a first bottom surface; and
forming the alignment mark comprises forming the alignment mark comprising an alignment mark bottom surface that is coplanar with the first bottom surface.
4. The method of claim 1 further comprising:
forming a first component from the first layer, wherein the first component and the second component form at least a portion of a planar waveguide.
5. The method of claim 4 wherein forming the first component comprises forming the first component with a first refractive index greater than a second refractive index of the second component.
6. The method of claim 1 further comprising:
patterning the first layer to form a first component prior to forming the second layer.
7. The method of claim 6 wherein patterning the first layer to form the first component comprises:
aligning a first mask overlying the first layer using the alignment mark.
8. The method of claim 1 further comprising:
forming a first component from the first layer wherein the second component overlies the first component.
9. The method of claim 1 further comprising:
viewing the alignment mark to position the second component; and
aligning a second mask over the second layer with the alignment mark.
10. The method of claim 1 further comprising:
forming a third layer overlying the second component.
11. The method of claim 1 wherein:
forming the alignment mark comprises forming the alignment mark wherein the alignment mark has an alignment mark transparency less than a first layer transparency.
12. The method of claim 11 wherein:
forming the alignment mark comprises forming the alignment mark wherein the alignment mark transparency is less than a second layer transparency.
13. The method of claim 1 wherein:
forming the alignment mark comprises forming the alignment mark with an alignment mark height less than a first layer height.
14. A method of producing an integrated circuit comprising:
forming a base layer overlying a substrate;
forming a first component overlying the base layer; and
forming a second component overlying the base layer, wherein forming the second component comprises aligning the second component with the first component by viewing an alignment mark through a first layer and a second layer, wherein the first layer and the second layer have a first refractive index and a second refractive index, respectively, that are within about 0.05 units of each other.
15. The method of claim 14 wherein forming the second component comprises viewing the alignment mark through the first layer and the second layer wherein the first layer and the second layer have a combined thickness of from about 2 to about 50 micrometers.
16. The method of claim 14 wherein forming the second component comprises:
aligning the second component with the first component by viewing the alignment mark, wherein the alignment mark comprises an alignment mark bottom surface that is coplanar with a first component bottom surface.
17. The method of claim 14 further comprising:
forming a third layer overlying the first component and the second component.
18. The method of claim 14 wherein forming the first component and forming the second component comprises forming a planar waveguide.
19. An integrated circuit comprising:
a substrate;
a base layer overlying the substrate;
a first component overlying the base layer, wherein the first component comprises a first refractive index measured at 589 nanometers, and the first component comprises a first bottom surface;
an alignment mark overlying the base layer, wherein the alignment mark comprises an alignment mark bottom surface that is co-planar with the first bottom surface; and
a second component overlying the base layer, wherein the second component directly contacts the first component, wherein the second component comprises a second refractive index measured at 589 nanometers, and wherein the second refractive index is within about 0.05 units of the first refractive index.