Memory cell structure and method for fabrication thereof
View Patent ↗A memory cell includes a substrate, an access transistor and a storage capacitor. The access transistor comprising a gate stack disposed on the substrate, and a first and second diffusion region located on a first and second opposing sides of the gate stack. The storage capacitor comprises a first capacitor plate comprising a portion embedded within the substrate below the first diffusion region, a second capacitor plate and a capacitor dielectric sandwiched between the embedded portion of the first capacitor plate. At least a portion of the first diffusion region forms the second capacitor plate.
1. A memory cell comprising:
a substrate;
an access transistor comprising a gate stack disposed on the substrate, and a first and second diffusion regions located on a first and second opposing sides of the gate stack; and
a storage capacitor comprising
a first capacitor plate including a first embedded portion within the substrate below the first diffusion region,
a second capacitor plate,
a capacitor dielectric sandwiched between the first embedded portion of the first capacitor plate and the second capacitor plate, the capacitor dielectric surrounds the first embedded portion of the first capacitor plate, and
wherein at least a portion of the first diffusion region forms the second capacitor plate.
2. The memory cell of claim 1 , wherein the first diffusion region comprises one of a source or drain region of the access transistor and the second diffusion region comprises the other of the source or drain region of the access transistor.
3. The memory cell of claim 1 , wherein the first embedded portion of the first capacitor plate comprises a cavity embedded within the substrate and filled with an electrode material, the capacitor dielectric lining the sidewalls of the cavity.
4. The memory cell of claim 1 , wherein the first embedded portion of the first capacitor plate substantially overlaps the first diffusion region.
5. The memory cell of claim 1 , the first capacitor plate further comprises a second embedded portion that is located underneath the first embedded portion and spaced therefrom.
6. The memory cell of claim 1 , further comprising a first trench isolation structure located in the substrate adjacent to the first embedded portion of the first capacitor plate wherein the first trench isolation structure isolates the memory cells from other device regions.
7. A memory cell comprising:
a substrate;
an access transistor comprising a gate stack disposed on the substrate, and a first and second diffusion regions located on a first and second opposing sides of the gate stack; and
a storage capacitor comprising
a first capacitor plate including a first embedded portion within the substrate below the first diffusion region,
a second capacitor plate,
a capacitor dielectric sandwiched between the first embedded portion of the first capacitor plate and the second capacitor plate, the capacitor dielectric surrounds the first embedded portion of the first capacitor plate, and wherein at least a portion of the first diffusion region forms the second capacitor plate; and
a first trench isolation structure located in the substrate adjacent to the first embedded portion of the first capacitor plate wherein the first trench isolation structure isolates the memory cell from other device regions.
8. The memory cell of claim 7 , wherein the first capacitor plate further comprises a second portion overlying the first trench isolation structure, the second portion folding under the first diffusion region to form the first embedded portion of the first capacitor plate.
9. The memory cell of claim 8 , wherein the first embedded portion of the first capacitor plate comprises a cavity embedded within the substrate and filled with an electrode material, the capacitor dielectric lining the sidewalls of the cavity.
10. A method for fabricating a memory cell comprising:
providing a substrate with a device region defined thereon;
forming a first capacitor plate comprising a portion embedded within the substrate in the device region;
forming a capacitor dielectric in the device region; and
forming an access transistor in the device region, the access transistor comprising a gate stack disposed on the substrate, and a first and second diffusion region located on a first and second opposing sides of the gate stack,
wherein at least a portion of the first diffusion region acts as a second capacitor plate and the capacitor dielectric is sandwiched between the embedded portion of the first capacitor plate and the second capacitor plate, and
wherein the capacitor dielectric surrounds the embedded portion of the first capacitor plate.
11. The method of claim 10 , wherein forming the first capacitor plate comprises forming a first buried region in a subsurface region of the substrate in the device region and selectively etching the first buried region to form a cavity embedded within the substrate.
12. The method of claim 10 , wherein the first diffusion region comprises one of a source or drain region of the access transistor and the second diffusion region comprises the other of the source or drain region of the access transistor.
13. The method of claim 10 , wherein the first capacitor plate further comprises a second embedded portion that is located underneath the first embedded portion and spaced therefrom.
14. The method of claim 10 , further comprising forming a first trench isolation structure in the substrate adjacent to the embedded portion of the first capacitor plate to isolate the device region from other device regions.
15. The method of claim 11 , further comprising forming a capacitor dielectric that lines the sidewalls of the cavity and thereafter depositing an electrode layer over the device region, the electrode layer filling the cavity.
16. The method of claim 15 , further comprising patterning the electrode layer to define the first capacitor plate and a gate electrode for the gate stack.
17. A method for fabricating a memory cell comprising:
providing a substrate with a device region defined thereon;
forming a first capacitor plate comprising a portion embedded within the substrate in the device region;
forming a capacitor dielectric in the device region;
forming a first trench isolation structure in the substrate adjacent to the embedded portion of the first capacitor plate to isolate the device region from other device regions; and
forming an access transistor in the device region, the access transistor comprising a gate stack disposed on the substrate, and a first and second diffusion region located on a first and second opposing sides of the gate stack,
wherein at least a portion of the first diffusion region acts as a second capacitor plate and the capacitor dielectric is sandwiched between the embedded portion of the first capacitor plate and the second capacitor plate.
18. The method of claim 17 , wherein forming the first trench isolation structure comprises:
forming a trench in the substrate; and
filling the trench with an isolation filler material to form the first trench isolation structure.
19. The method of claim 18 , wherein forming the first capacitor plate comprises forming a first buried region in a subsurface region of the substrate in the device region and selectively etching the first buried region to form a cavity embedded within the substrate.
20. The method of claim 18 , wherein the isolation filler material has a lower density at regions proximate a corner of the trench.
21. The method of claim 19 , wherein at least a portion of the first buried region is exposed while forming the trench in the substrate.
22. The method of claim 21 , further comprising etching the first buried region to form the cavity after forming the trench in the substrate.