Low cost high performance EEPROM device
Devices and methods for forming a device are presented. The method includes providing a substrate prepared with a cell area separated by other active areas by isolation regions. First and second lower sub-gates of first and second transistors are formed in the cell area. A common upper sub-gate of the first and second transistors is formed. The common upper sub-gate and first and second lower sub-gates are separated by an intergate dielectric layer and the common upper sub-gate surrounds the first and second lower sub-gates.
1. A device comprising:
a substrate prepared with a cell area separated by other active areas by isolation regions; and
first and second transistors disposed in the cell area, wherein the first and second transistors comprise
first and second lower sub-gates disposed over the substrate, and
a common upper sub-gate disposed over the first and second lower sub-gates, wherein the common upper sub-gate is separated from the first and second lower sub-gates by an intergate dielectric layer and the common upper sub-gate surrounds the first and second lower sub-gates.
2. The device of claim 1 comprising a gate dielectric layer that separates the first lower sub-gate from a channel of the first transistor and the second lower sub-gate from a channel of the second transistor, wherein the gate dielectric layer comprises a tunneling window under the first lower sub-gate.
3. The device of claim 2 comprising first and second intermediately doped buried regions disposed in the substrate, wherein the buried doped regions extend beneath the first lower sub-gate.
4. The device of claim 1 wherein the common upper sub-gate is a single and continuous gate layer covering the first and second lower sub-gates.
5. The device of claim 1 comprising first and second doped regions disposed adjacent to the first and second transistors that form source/drain (S/D) diffusion regions of the first and second transistors.
6. The device of claim 5 wherein the first doped region is common to both the first and second transistors.
7. The device of claim 6 comprising lightly doped first sub-portions disposed in the first and second doped regions of the first and second transistors, wherein the first sub-portions are self-aligned to the lower sub-gates.
8. The device of claim 7 comprising heavily doped second sub-portions in the second doped regions of the first and second transistors adjacent to first and second sidewalls of the common upper sub-gate, wherein the second sub-portions have a depth shallower than the first sub-portions.
9. The device of claim 8 wherein a portion of the substrate between the first and second lower sub-gates is devoid of a heavily doped second sub-portion.
10. The device of claim 1 comprising a first contact which couples a portion of the common upper sub-gate above the first lower sub-gate to a control gate line and a second contact which couples the second lower sub-gate to a wordline of the memory cell.
11. The device of claim 1 wherein the intergate dielectric layer is common to the first and second transistors and comprises a dielectric stack having multiple dielectric layers.
12. The device of claim 2 wherein the gate dielectric layer comprises thermal silicon oxide.
13. The device of claim 4 comprising first and second contacts in a premetal dielectric layer to couple to first and second cell terminals.
14. The device of claim 13 comprising a third contact which couples a portion of the common upper sub-gate above the first lower sub-gate to a control gate line and a fourth contact which couples the second lower sub-gate to a wordline.
15. The device of claim 13 comprising a third contact which couples a portion of the common upper sub-gate above the first lower sub-gate and a fourth contact is coupled to the second lower sub-gate and is isolated from the common upper sub-gate.
16. The device of claim 15 wherein a portion of the second lower sub-gate are exposed and extended beyond the common upper sub-gate.
17. The device of claim 5 wherein the second doped region comprises first and second sub-portions while the first doped region comprises a first sub-portion and is devoid of a second sub-portion.
18. A device comprising:
a substrate prepared with a cell area separated by other active areas by isolation regions;
first and second lower sub-gates of first and second transistors in the cell area;
a gate dielectric layer that separates the first lower sub-gate from a channel of the first transistor and the second lower sub-gate from a channel of the second transistor, wherein the gate dielectric layer comprises a tunneling window under the first lower sub-gate;
a common upper sub-gate of the first and second transistors, wherein the common upper sub-gate and the first and second lower sub-gates are separated by an intergate dielectric layer and the common upper sub-gate surrounds the first and second lower sub-gates; and
first and second intermediately doped buried regions in the substrate, wherein the buried doped regions extend beneath the first lower sub-gate.
19. The device of claim 18 comprising first and second doped regions adjacent to the first and second transistors that form source/drain (S/D) diffusion regions of the first and second transistors.
20. The device of claim 18 comprising a first contact which couples a portion of the common upper sub-gate above the first lower sub-gate to a control gate line and a second contact which couples the second lower sub-gate to a wordline of the memory cell.