Magnetic shielding for MTJ device or bit
Emerging memory chips and methods for forming an emerging memory chip are presented. For example, magnetic random access memory (MRAM) chip magnetic shielding at the device-level is disclosed. The MRAM chip includes a magnetic shield structure that is substantially surrounding a magnetic tunnel junction (MTJ) bit or device of a MTJ array. The magnetic shield may be configured in the form of a cylindrical shield structure or magnetic shield spacer that substantially surrounds the MTJ bit or device. The magnetic shield structure in the form of cylindrical shield structure or magnetic shield spacer may include top and/or bottom plate shield. The magnetic shield structure in various forms and configurations protect the MTJ stack from external or local magnetic fields. This magnetic shielding structure is applicable for both in-plane and perpendicular MRAM chips.
1. A magnetic random access memory (MRAM) chip comprising:
a substrate having first and second surfaces, wherein the first surface is defined with a MRAM region;
an upper inter level dielectric (ILD) layer disposed over the first surface of the substrate, wherein the upper ILD layer comprises a plurality of ILD levels;
a magnetic storage element having a magnetic tunneling junction (MTJ) array with MTJ stack disposed in between top and bottom electrodes in the MRAM region, wherein the magnetic storage element is disposed in a dielectric layer in between adjacent ILD levels of the upper ILD layer;
at least a magnetic shield structure disposed in the same dielectric layer as the MTJ stack, wherein the magnetic shield structure is in the form of a side shield structure with a top plate shield that substantially surrounds the MTJ stack, wherein the top plate shield is in contact with the side shield structure, and wherein the side shield structure and the top plate shield include a same magnetic shield material; and
a pad level disposed over the magnetic storage element, wherein the pad level comprises a die bond/bump pad coupled to the magnetic storage element.
2. The MRAM chip of claim 1 wherein the side shield structure is in the form of a cylindrical side shield structure that substantially surrounds the MTJ stack.
3. The MRAM chip of claim 2 wherein the cylindrical side shield structure is isolated from the MTJ by a portion of dielectric material of the dielectric layer.
4. The MRAM chip of claim 2 wherein:
the top electrode comprises a lower top electrode portion and an upper top electrode portion; and wherein the top plate shield is disposed in between the lower and upper top electrode portions of the top electrode.
5. The MRAM chip of claim 4 wherein outer edge of the top plate shield is aligned with outer edge of the cylindrical side shield structure of the magnetic shield structure.
6. The MRAM chip of claim 4 wherein outer edge of the top plate shield extends beyond outer edge of the cylindrical side shield structure of the magnetic shield structure.
7. The MRAM chip of claim 4 wherein:
the magnetic shield structure further comprises a bottom plate shield that is disposed below the MTJ stack.
8. The MRAM chip of claim 1 comprising an encapsulation liner which lines exposed sidewalls of the MTJ stack.
9. The MRAM chip of claim 8 wherein the side shield structure is in the form of a magnetic shield spacer that substantially surrounds the MTJ stack, and wherein the magnetic shield spacer abuts sidewall of the encapsulation liner.
10. The MRAM chip of claim 1 wherein:
the top electrode comprises a lower top electrode portion and an upper top electrode portion; and wherein the top plate shield is disposed in between the lower and upper top electrode portions of the top electrode.
11. The MRAM chip of claim 10 wherein:
the magnetic shield structure further comprises a bottom plate shield that is disposed below the MTJ stack.
12. The MRAM chip of claim 1 wherein the magnetic shield material includes Nickel (Ni), Iron (Fe) or Nickel-Iron alloy (NiFe).
13. A magnetic random access memory (MRAM) chip comprising:
a substrate having first and second surfaces, wherein the first surface is defined with a MRAM region;
an upper inter level dielectric (ILD) layer disposed over the first surface of the substrate, wherein the upper ILD layer comprises a plurality of ILD levels;
a magnetic storage element having a magnetic tunneling junction (MTJ) array with MTJ stack disposed in between top and bottom electrodes in the MRAM region, wherein the magnetic storage element is disposed in a dielectric layer in between adjacent ILD levels of the upper ILD layer; and
at least a magnetic shield structure disposed in the same dielectric layer as the MTJ stack, wherein the magnetic shield structure comprises a bottom magnetic shield covering the MTJ stack and a side magnetic shield substantially surrounding the MTJ stack, and wherein the bottom magnetic shield is disposed below the MTJ stack in a trench which accommodates the bottom electrode, and wherein the bottom magnetic shield and the side magnetic shield include a same magnetic shield material.
14. The MRAM chip of claim 13 wherein the side magnetic shield is in the form of a cylindrical side magnetic shield that surrounds the MTJ stack; and
is isolated from the MTJ by a portion of dielectric material of the dielectric layer.
15. The MRAM chip of claim 14 wherein the magnetic shield structure further comprises a top magnetic shield, and wherein the top magnetic shield is a substantially planarized top plate shield that disposed between a lower top electrode portion and an upper top electrode portion of the top electrode.
16. The MRAM chip of claim 13 further comprises an encapsulation liner disposed over exposed sidewalls of the MTJ stack and exposed surface of the bottom electrode.
17. The MRAM chip of claim 16 wherein the side magnetic shield
is disposed over the encapsulation liner; and
is in the form of magnetic shield spacer that substantially surrounds the MTJ stack.
18. The MRAM chip of claim 17 wherein the top magnetic shield is a substantially planarized top plate shield that disposed between a lower top electrode portion and an upper top electrode portion of the top electrode.
19. The MRAM chip of claim 13 wherein the magnetic shield structure includes Nickel (Ni), Iron (Fe) or Nickel-Iron alloy (NiFe).
20. A magnetic random access memory (MRAM) chip comprising:
a substrate having first and second surfaces, wherein the first surface is defined with a MRAM region;
an upper inter level dielectric (ILD) layer disposed over the first surface of the substrate, wherein the upper ILD layer comprises a plurality of ILD levels;
a magnetic storage element having a magnetic tunneling junction (MTJ) array with MTJ stack disposed in between top and bottom electrodes in the MRAM region, wherein the magnetic storage element is disposed in a dielectric layer in between adjacent ILD levels of the upper ILD layer, and wherein the top electrode comprises a lower top electrode portion and an upper top electrode portion; and
at least a magnetic shield structure disposed in the same dielectric layer as the MTJ stack, wherein the magnetic shield structure is in the form of a side shield structure with a top plate shield that substantially surrounds the MTJ stack, and wherein the top plate shield is disposed in between the lower and upper top electrode portions of the top electrode.