Spacer-less low-K dielectric processes
View Patent ↗A first example embodiment provides a method of removing first spacers from gates and incorporating a low-k material into the ILD layer to increase device performance. A second example embodiment comprises replacing the first spacers after silicidation with low-k spacers. This serves to reduce the parasitic capacitances. Also, by implementing the low-k spacers only after silicidation, the embodiments' low-k spacers are not compromised by multiple high dose ion implantations and resist strip steps. The example embodiments can improve device performance, such as the performance of a rim oscillator.
1. A semiconductor device comprising:
a substrate prepared with a device region;
a transistor in the device region, the transistor includes a gate stack on the substrate and source/drain (S/D) diffusion regions adjacent to the gate stack, the S/D regions include main S/D portions and offset S/D portions, the offset S/D portions are adjacent to exposed gate sidewalls of the gate stack and the main S/D portions are distal from the exposed gate sidewalls separated by the offset S/D portions;
a patterned dielectric layer disposed over the device region on the main S/D portions without covering the offset S/D portions; and
an etch stop layer over the substrate in the device region, the etch stop layer covering the gate stack and S/D regions, including the patterned dielectric layer.
2. The device of claim 1 comprises silicide contacts in the main S/D portions below the patterned dielectric layer.
3. The device of claim 1 comprises a ring oscillator device.
4. The device of claim 1 wherein the patterned dielectric layer does not cover a top of the gate stack.
5. The device of claim 1 wherein the etch stop layer comprises a low k etch stop layer.
6. The device of claim 5 comprises low k dielectric sidewall spacers disposed on the etch stop layer on sidewalls of the gate stack.
7. The device of claim 5 comprises:
a low k dielectric layer over the device region covering the etch stop layer; and
interconnects to the S/D regions.
8. A semiconductor device comprises:
a substrate having a FET region and a peripheral region;
a first transistor in the FET region, wherein the first transistor comprises
a first gate with first gate sidewalls, and
first S/D regions adjacent to the first gate, wherein the S/D regions include first main S/D portions and first offset S/D portions, the first offset S/D portions are adjacent to the first gate sidewalls and the first main S/D portions are distal from the first gate sidewalls separated by the first offset S/D portions;
peripheral gate structures on the substrate in the peripheral region;
a patterned dielectric layer disposed over FET region on the first main S/D portions and not on the first gate sidewalls and the offset S/D portions of the source/drain regions; and
an etch stop layer over the substrate in the FET and peripheral regions, the etch stop layer covering the first gate and S/D regions, including the patterned dielectric layer and the peripheral gate structures.
9. The device of claim 8 comprises silicide contacts in the first main S/D portions below the patterned dielectric layer.
10. The device of claim 8 comprises a ring oscillator device.
11. The device of claim 8 wherein the patterned dielectric layer does not cover a top of the first gate.
12. The device of claim 8 wherein the etch stop layer comprises a low k etch stop layer.
13. The device of claim 12 comprises low k dielectric sidewall spacers disposed on the etch stop layer on the first gate sidewalls of the first gate.
14. The device of claim 13 comprises:
a low k dielectric layer over the device region covering the etch stop layer; and
interconnects to the S/D regions.
15. A device comprising:
a substrate with a transistor, wherein the transistor includes
a gate stack on the substrate, and
S/D regions adjacent to the gate stack, the S/D regions include main S/D portions and offset S/D portions, the offset S/D portions are adjacent to exposed gate sidewalls of the gate stack and the main S/D portions are separated from the exposed gate sidewalls by the offset S/D portions;
a patterned dielectric layer disposed over device region on the main S/D portions without covering the offset S/D portions; and
an etch stop layer over the substrate in the device region, the etch stop layer covering the gate stack and S/D regions, including the patterned dielectric layer.
16. The device of claim 15 wherein the etch stop layer comprises a low k etch stop layer.
17. The device of claim 16 comprises low k dielectric sidewall spacers disposed on the etch stop layer on sidewalls of the gate stack.
18. The device of claim 15 comprises:
a low k dielectric layer over the device region covering the etch stop layer; and
interconnects to the S/D regions.