IP Library Granted Patent US 9,048,129
Granted Patent B2
US 9,048,129 · App. 13/115,684 · Granted Jun 2, 2015

Method for forming fully relaxed silicon germanium on silicon

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,048,129
App. No.
13/115,684
Granted
Jun 2, 2015
Kind
B2
Abstract

Semiconductor devices are formed with a thin layer of fully strain relaxed epitaxial silicon germanium on a substrate. Embodiments include forming a silicon germanium (SiGe) epitaxial layer on a semiconductor substrate, implanting a dopant into the SiGe epitaxial layer, and annealing the implanted SiGe epitaxial layer.

Claims (26)

1. A method comprising:

forming a silicon germanium (SiGe) epitaxial layer having a thickness less than 200 nm on a semiconductor substrate;

ion implanting a dopant into the SiGe epitaxial layer; and

annealing the implanted SiGe epitaxial layer at a temperature of 400° C. to 1350° C.,

wherein the annealed SiGe has a threading dislocation density less than 1e6/cm2, and

wherein the annealed SiGe has a degree of strain relaxation greater than 90%.

2. The method according to claim 1 , comprising forming the SiGe epitaxial layer on a single crystalline silicon substrate.

3. The method according to claim 1 , comprising forming the SiGe epitaxial layer on a silicon-on-insulator (SOI) substrate.

4. The method according to claim 1 , comprising implanting arsenic (As), germanium (Ge), or boron (B) into the SiGe epitaxial layer.

5. The method according to claim 1 , comprising forming the SiGe epitaxial layer with 10 atomic % to near 100 atomic % Ge.

6. The method according to claim 1 , comprising annealing the implanted SiGe epitaxial layer by rapid thermal anneal or a furnace anneal.

7. The method according to claim 1 , comprising forming the SiGe epitaxial layer on the semiconductor substrate by blanket epitaxy.

8. The method according to claim 1 , comprising forming the SiGe epitaxial layer on the semiconductor substrate by selective epitaxy.

9. A device comprising:

a semiconductor substrate; and

a SiGe epitaxial layer having a thickness less than 200 nm, implanted with a dopant, formed on the semiconductor substrate,

wherein the implanted SiGe epitaxial layer has a degree of strain relaxation greater than 90% and wherein the implanted SiGe epitaxial layer has a threading dislocation density less than 1e6/cm2.

10. The device according to claim 9 , wherein the dopant comprises As, Ge, or B.

11. The device according to claim 9 , wherein the SiGe epitaxial layer comprises 10 atomic % to near 100 atomic % Ge.

12. A method comprising:

epitaxially growing asilicon germanium (SiGe) layer to a thickness less than 100 nm on a silicon or silicon-on-insulator (SOI) substrate, the SiGe having 10 atomic % to near 100 atomic % Ge;

ion implanting a dopant at a dose of 1E11/cm2 to 2E15/cm2 into the SiGe layer; and

thermally annealing the implanted SiGe epitaxial layer at a temperature of 400° C. to 1350° C.,

wherein the annealed SiGe layer has a threading dislocation density less than 1e6/cm2, and a degree of strain relaxation greater than 90%.

13. The method according to claim 12 , comprising implanting arsenic (As) into the SiGe layer.

14. The method according to claim 12 , comprising implanting germanium (Ge) into the SiGe layer.

Assignments (2)
RELEASE OF SECURITY INTEREST Recorded Nov 19, 2020
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
Reel/Frame 054481/0673 →
SECURITY AGREEMENT Recorded Nov 27, 2018
From: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
To: WILMINGTON TRUST, NATIONAL ASSOCIATION
Reel/Frame 047660/0203 →