RRAM structure at STI with Si-based selector

1. A device comprising:

a substrate;

a well of a first polarity in the substrate;

a shallow trench isolation (STI) region formed in the substrate extending partially into the well;

bands of a second polarity in the substrate, over the well, at opposite sides of the STI region;

an area of the first polarity at a top surface of the substrate over each band;

an area of the second polarity in the substrate over each band, adjacent each area of the first polarity and remote from the STI region;

a recess in a top portion of the STI region, wherein a bottom surface of the recess is above a top surface of the band;

a resistive random access memory (RRAM) liner on side and bottom surfaces of the recess; and

a top electrode in the recess.

2. The device according to claim 1 , wherein the RRAM liner comprises an oxide of a transition metal.

3. The device according to claim 1 , wherein a thickness of the RRAM liner is 3 nm to 900 nm.

4. The device according to claim 1 , wherein the top electrode comprises a transition metal, titanium nitride (TiN), TiN/Ti, or polysilicon.

5. The device according to claim 1 , further comprising silicon nitride (SiN) spacers at opposite sides of the top electrode.

6. The device according to claim 1 , wherein the STI region has a depth of 100 to 1000 nm.

7. The device according to claim 1 , wherein the STI region comprises silicon dioxide (SiO 2 ), silicon nitride (Si 3 N 4 ) or silicon oxynitride (SiON).

8. The device according to claim 1 , wherein the well is implanted with phosphorus (P) or arsenic (As).

9. The device according to claim 8 , wherein the band of a second polarity is implanted with boron (B), boron difluoride (BF 2 ), or indium (In).

10. A device comprising:

a substrate;

plural wells of a first polarity in the substrate;

shallow trench isolation (STI) regions formed in the substrate, parallel to and separated from each other, each STI region extending partially into a different one of the plural wells;

bands of a second polarity in the substrate, over the wells, at opposite sides of each STI region;

first and second areas of the first polarity at a top surface of the substrate over each band, at opposite sides of each STI region;

first and second areas of the second polarity in the substrate over each band, adjacent the first and second areas, respectively, of the first polarity and remote from the corresponding STI region;

a recess in a top portion of each STI region, wherein a bottom surface of each recess is above a top surface of each band;

a resistive random access memory (RRAM) liner on side and bottom surfaces of each recess; and

a top electrode in each recess.

11. The device according to claim 10 , wherein each RRAM liner comprises an oxide of a transition metal.

12. The device according to claim 10 , wherein a thickness of each RRAM liner is 3 nm to 900 nm.

13. The device according to claim 10 , wherein the top electrode comprises a transition metal, titanium nitride (TiN), TiN/Ti, or polysilicon.

14. The device according to claim 10 , further comprising silicon nitride (SiN) spacers at opposite sides of each top electrode.

15. The device according to claim 10 , wherein each STI region has a depth of 100 to 1000 nm.

16. The device according to claim 10 , wherein each STI region comprises silicon dioxide (SiO 2 ), silicon nitride (Si 3 N 4 ) or silicon oxynitride (SiON).

17. The device according to claim 10 , wherein each well is implanted with phosphorus (P) or arsenic (As).

18. The device according to claim 17 , wherein each band of a second polarity is implanted with boron (B), boron difluoride (BF 2 ), or indium (In).

19. The device according to claim 10 , further comprising:

first and second bit lines connected to the first and second areas of second polarity, respectively;

first and second word lines connected to first and second columns of top electrodes, respectively;

and a select line formed in the wells.

20. A device comprising:

a substrate;

plural wells of a first polarity in the substrate;

shallow trench isolation (STI) regions formed in the substrate, parallel to and separated from each other, each STI region extending partially into a different one of the plural wells;

bands of a second polarity in the substrate, over the wells, at opposite sides of each STI region;

first and second areas of the first polarity at a top surface of the substrate over each band, at opposite sides of each STI region;

first and second areas of the second polarity in the substrate over each band, adjacent the first and second areas of the first polarity, respectively, and remote from the corresponding STI region;

a recess in a top portion of each STI region, wherein a bottom surface of each recess is above a top surface of each band;

a resistive random access memory (RRAM) liner comprising an oxide of a transition metal having a thickness of 3 nm to 900 nm on side and bottom surfaces of each recess;

a top electrode comprising a transition metal, titanium nitride (TiN), TiN/Ti, or polysilicon in each recess;

silicon nitride (SiN) spacers at opposite sides of each top electrode;

first and second bit lines connected to the first and second areas of second polarity, respectively;

first and second word lines connected to first and second columns of top electrodes, respectively; and

a select line formed in the wells.