Integrated circuit system with double doped drain transistor
View Patent ↗An integrated circuit system includes a substrate, forming a gate over the substrate, forming a first drift region having a first counter diffused region and a source diffused region, the first drift region in the substrate adjacent a first side of the gate, and forming a second drift region having a second counter diffused region and a drain diffused region, the second drift region in the substrate adjacent a second side of the gate opposite the first side of the gate.
1. A method of manufacturing an integrated circuit comprising:
providing a substrate;
forming a gate over the substrate;
forming a first drift region in the substrate adjacent to a first side of the gate;
forming a first counter diffused region, to a depth less than a depth of the first drift region, for forming a bipolar-like junction with the first drift region; and
forming a source diffused region, in the first drift region and separated from the first counter diffused region, near a side of the first counter diffused region located further from the gate.
2. The method as claimed in claim 1 further comprising flowing current through the first drift region and a bulk region of the substrate.
3. The method as claimed in claim 1 wherein forming the first counter diffused region includes doping the first drift region and the gate.
4. The method as claimed in claim 1 wherein forming the first counter diffused region includes doping the first drift region.
5. The method as claimed in claim 1 wherein forming the first counter diffused region includes forming the first counter diffused region at a depth approximately half a depth of the first drift region.
6. A method of manufacturing an integrated circuit comprising:
providing a substrate having a bulk region;
forming a gate with a gate insulator over the substrate;
forming a first drift region in the substrate adjacent a first side of the gate;
forming a second drift region in the substrate adjacent a second side of the gate opposite the first side of the gate;
forming a first counter diffused region in the first drift region, to a depth less than a depth of the first drift region, for forming a bipolar-like junction with the first drift region;
forming a second counter diffused region, in the second drift region, adjacent the second side of the gate for forming the bipolar-like junction with the second drift region;
forming a source diffused region, in the first drift region, adjacent a side of the first counter diffused region opposite the first side of the gate; and
forming a drain diffused region, in the second drift region and separated from the first counter diffused region, near a side of the second counter diffused region located further from the gate.
7. The method as claimed in claim 6 wherein forming the first counter diffused region includes forming the first counter diffused region to a depth of approximately one-tenth of a micron to three-tenths of a micron.
8. The method as claimed in claim 6 wherein forming the first counter diffused region includes boron or a compound thereof.
9. The method as claimed in claim 6 wherein forming the first counter diffused region includes phosphorus, arsenic, antimony, or a compound thereof.
10. The method as claimed in claim 6 wherein forming the first counter diffused region includes forming the first counter diffused region with a dopant concentration approximately an order of magnitude less than a dopant concentration of the first drift region.
11. An integrated circuit system comprising:
a substrate;
a gate over the substrate;
a first drift region formed in the substrate adjacent to a first side of the gate;
a first counter diffused region formed in the first drift region, to a depth less than a depth of the first drift region, to form a bipolar-like junction with the first drift region; and
a source diffused region, formed in the first drift region and separated from the first counter diffused region, near a side of the first counter diffused region located further from the gate.
12. The system as claimed in claim 11 wherein the first counter diffused region includes the first counter diffused region at a depth approximately half a depth of the first drift region.
13. The system as claimed in claim 11 further comprising the first drift region and a bulk region of the substrate for current flow.
14. The system as claimed in claim 11 wherein the first drift region surrounds the first counter diffusion region formed by a dopant in the first drift region and self-aligned to the gate.
15. The system as claimed in claim 11 wherein the source diffused region is formed by a dopant in the first drift region.
16. The system as claimed in claim 11 further comprising:
a bulk region in the substrate;
a gate insulator over the substrate;
a second drift region formed in the substrate adjacent to a second side of the gate opposite the first side of the gate;
a second counter diffused region, formed in the second drift region, adjacent the second side of the gate to form the bipolar-like junction with the second drift region; and;
a drain diffused region, formed in the second drift region and separated from the second counter diffused region, near a side of the second counter diffused region located further from the gate.
17. The system as claimed in claim 16 wherein the first counter diffused region includes the first counter diffused region to a depth of approximately one-tenth of a micron to three-tenths of a micron.
18. The system as claimed in claim 16 wherein the first counter diffused region includes boron or a compound thereof.
19. The system as claimed in claim 16 wherein the first counter diffused region includes phosphorus, arsenic, antimony, or a compound thereof.
20. The system as claimed in claim 16 wherein the first counter diffused region includes the first counter diffused region with a dopant concentration approximately an order of magnitude less than a dopant concentration of the first drift region.