Methods for fabricating device substrates and integrated circuits
View Patent ↗Methods for fabricating device substrates are provided where the device substrates have rounded trench corners in medium voltage (MV) and high voltage (HV) regions thereof to minimize interference with performance of MV or HV devices adjacent thereto. The fabricating methods involve thermally oxidizing a trench-forming area in an MV or HV region on a semiconductor substrate to form a silicon oxide layer having narrowed birds beak edges that create rounded trench shoulders semiconductor substrate. An isolation trench is then formed through the silicon oxide layer, into the semiconductor substrate, removing portion of the silicon oxide layer and leaving the birds beak edges. After removing the birds beak edges, an oxide layer is formed lining the trench and shoulders to create rounded trench corners in the MV or HV region. Trenches having rounded corners may be formed simultaneously with forming trenches in low voltage regions that don't have rounded trench corners.
1. A method for fabricating a device substrate, the method comprising the steps of:
providing a semiconductor substrate with a substrate surface and having a low voltage (LV) region and a second voltage region that is either a medium voltage (MV) region or a high voltage (HV) region;
thermally oxidizing a trench-forming area on the substrate surface in the second voltage region to form a silicon oxide layer, wherein the silicon oxide layer has birds beak edges that extend in opposite directions and form rounded trench shoulders of the semiconductor substrate in the second voltage region;
forming an LV trench in the semiconductor substrate in the LV region such that the semiconductor substrate has an LV shoulder;
forming a trench in the silicon oxide layer and semiconductor substrate in the second voltage region such that the semiconductor substrate has a rounded trench shoulder adjacent a birds beak edge;
removing the birds beak edge in the second voltage region; and
forming an oxide layer lining each of the LV trench and LV shoulder in the LV region, wherein the LV shoulder and the oxide layer thereon form an LV trench corner; and
forming an oxide layer lining each of the trench and rounded trench shoulder in the second voltage region, wherein the rounded trench shoulder in the second voltage region and oxide layer thereon form a rounded trench corner in the second voltage region that is more rounded than the LV corner.
2. The method of claim 1 , wherein the rounded trench corner in the second voltage region is sufficiently rounded to minimize interference with performance of voltage devices to be formed adjacent thereto.
3. The method of claim 1 , wherein after forming the oxide layers in the LV region and the second voltage region, respectively, the LV trench corner has a radius of curvature, R 1 , and the rounded trench corner in the second voltage region has a radius of curvature, R 2 , and wherein R 2 is at least 8% greater than R 1 .
4. The method of claim 1 , wherein the step of thermally oxidizing the trench-forming area also forms a rounded trench shoulder in the second voltage region that is capable, when lined with an oxide layer to form a rounded trench corner, of minimizing interference with performance of a medium or high voltage device adjacent thereto, wherein the medium or high voltage device has an operating voltage of at least about 5 V.
5. The method of claim 1 , wherein the steps of forming an LV trench in the LV region and forming a trench in second voltage region are performed simultaneously.
6. The method of claim 1 , wherein the steps of forming an oxide layer in each of the LV and second voltage regions, respectively, are performed simultaneously.
7. The method of claim 1 , wherein the steps of forming an oxide layer in each of the LV and second voltage regions, respectively, each forms an oxide layer having a thickness of from about 20 Angstroms (Å) to about 200 Å.
8. The method of claim 1 , wherein, after providing the semiconductor substrate, the method further comprises the steps of:
forming a pad nitride layer overlaying the semiconductor substrate; and
forming an LV furrow in the LV region that extends through the pad nitride layer to expose the LV trench-forming area on the substrate surface in the LV region, wherein the step of forming the LV trench is performed after formation of the furrow, and
forming a furrow in the second voltage region that extends through the pad nitride layer to expose the trench-forming area on the substrate surface in the second voltage region, wherein the steps of thermally oxidizing to form the silicon oxide layer and forming the trench in the second voltage region are performed after formation of the furrow.
9. The method of claim 8 , wherein the steps of forming an LV furrow in the LV region and forming a furrow in the second voltage region are each performed by etching.
10. The method of claim 8 , wherein, prior to forming the oxide layers lining the LV trench in the LV region and the trench in the second voltage region, the method further comprises the step of laterally recessing the pad nitride layer proximate the LV shoulder in the LV region and proximate the rounded trench shoulder in the second voltage region.
11. A method for fabricating a device substrate, the method comprising the steps of:
providing a semiconductor substrate with a substrate surface and having:
a low voltage (LV) region,
a second voltage region that is either a medium voltage (MV) region or a high voltage (HV) region, and
a third voltage region that is either a medium voltage (MV) region or a high voltage (HV) region;
thermally oxidizing a trench-forming area on the substrate surface in the second voltage region to form a silicon oxide layer, wherein the silicon oxide layer has birds beak edges that extend in opposite directions and form rounded trench shoulders of the semiconductor substrate in the second voltage region;
thermally oxidizing a trench-forming area on the substrate surface in the third voltage region to form a silicon oxide layer, wherein the silicon oxide layer has birds beak edges that extend in opposite directions and form rounded trench shoulders of the semiconductor substrate in the third voltage region;
forming an LV trench in the LV region by removing a portion of the semiconductor substrate from within an LV trench-forming area in the LV region such that the semiconductor substrate has an LV shoulder;
forming a trench in the second voltage region by removing a portion of the silicon oxide layer and a portion of the semiconductor substrate from within a trench-forming area in the second voltage region, but not removing the birds beak edges, wherein the semiconductor substrate has a rounded trench shoulder;
forming a trench in the third voltage region by removing a portion of the silicon oxide layer and a portion of the semiconductor substrate from within a trench-forming area in the third voltage region, but not removing the birds beak edges, wherein the semiconductor substrate has a rounded trench shoulder;
removing the birds beak edges in each of the second and third voltage regions; and
forming an oxide layer lining each of the LV trench and LV shoulder in the LV region, wherein the LV shoulder and the oxide layer thereon form an LV trench corner;
forming an oxide layer lining each of the trench and rounded trench shoulder in the second voltage region, wherein the rounded trench shoulder in the second voltage region and oxide layer thereon form a rounded trench corner in the second voltage region that is more rounded than the LV corner; and
forming an oxide layer lining each of the trench and rounded trench shoulder in the third voltage region, wherein the rounded trench shoulder in the third voltage region and oxide layer thereon form a rounded trench corner in the third voltage region that is more rounded than the LV corner.
12. The method of claim 11 , wherein after forming the oxide layers in the LV region and the second voltage region, respectively, the LV trench corner has a radius of curvature, R 1 , and the rounded trench corner in the second voltage region has a radius of curvature, R 2 , and wherein R 2 is at least 8% greater than R 1 .
13. The method of claim 11 , wherein the steps of forming an LV trench in the LV region, forming a trench in the second voltage region, and forming a trench in the third voltage region are performed simultaneously.
14. The method of claim 11 , wherein the steps of forming an oxide layer in each of the LV, second and third voltage regions, respectively, are performed simultaneously.
15. A method for fabricating an integrated circuit, the method comprising the steps of:
providing a semiconductor substrate with a substrate surface and having a low voltage (LV) region and a second voltage region that is either a medium voltage (MV) region or a high voltage (HV) region;
thermally oxidizing a trench-forming area on the substrate surface in the second voltage region to form a silicon oxide layer, wherein the silicon oxide layer has birds beak edges that extend in opposite directions and form rounded trench shoulders of the semiconductor substrate in the second voltage region;
forming an LV trench in the semiconductor substrate in the LV region such that the semiconductor substrate has an LV shoulder;
forming a trench in the silicon oxide layer and semiconductor substrate in the second voltage region such that the semiconductor substrate has a rounded trench shoulder adjacent a birds beak edge;
removing the birds beak edge in the second voltage region; and
forming an oxide layer lining each of the LV trench and LV shoulder in the LV region, wherein the LV shoulder and the oxide layer thereon form an LV trench corner;
forming an oxide layer lining each of the trench and rounded trench shoulder in the second voltage region, wherein the rounded trench shoulder in the second voltage region and oxide layer thereon form a rounded trench corner in the second voltage region that is more rounded than the LV corner;
forming an LV device having an operating voltage of no more than about 1.4 volts (V) in the LV region; and
forming an MV device or an HV device having an operating voltage of at least about 5 V in the second voltage region.
16. The method of claim 15 , wherein after forming the oxide layers in the LV region and the second voltage region, respectively, the LV trench corner has a radius of curvature, R 1 , and the rounded trench corner in the second voltage region has a radius of curvature, R 2 , and wherein R 2 is at least 8% greater than R 1 .
17. The method of claim 16 , wherein the steps of forming an LV trench in the LV region and forming a trench in second voltage region are performed simultaneously.
18. The method of claim 16 , wherein the steps of forming an oxide layer in each of the LV and second voltage regions, respectively, are performed simultaneously.
19. The method of claim 16 , wherein, after providing the semiconductor substrate, the method further comprises the steps of:
forming a pad oxide layer overlaying the substrate surface;
forming a pad nitride layer overlaying the pad oxide layer; and
forming an LV furrow in the LV region that extends through the pad nitride and pad oxide layers to expose the LV trench-forming area on the substrate surface in the LV region, wherein the step of forming the LV trench in the second voltage region is performed after formation of the furrow, and
forming a furrow in the second voltage region that extends through the pad nitride and pad oxide layers to expose the trench-forming area on the substrate surface in the second voltage region, wherein the steps of forming the oxide layer and forming the trench in the second voltage region are performed after formation of the furrow.
20. The method of claim 19 , wherein, prior to forming the oxide layers lining the LV trench and the trench in the second voltage region, the method further comprises the step of laterally recessing the pad nitride layer proximate the LV shoulder in the LV region and proximate the rounded trench shoulder in the second voltage region.