Integrated circuit having a plurality of MOSFET devices
View Patent ↗A method is provided for manufacturing an integrated circuit having a plurality of MOSFET devices, comprising the steps of: providing a plurality of MOSFET devices each having a first and a second structural parameter associated therewith, wherein a value of one of the first and a second structural parameter of each device is selected to provide a value of a performance parameter of the device substantially equal to a predetermined reference value, the predetermined reference value being the same for each device.
1. A method for manufacturing an integrated circuit comprising:
providing a first transistor comprising a first gate, first gate dielectric, first source/drain regions regions and a first channel region, the first gate being located at a first distance from a gate of a first adjacent transistor;
providing a second transistor comprising a second gate, second gate dielectric, a second source/drain regions region and a second channel region, the second gate being located at a second distance from a gate of a second adjacent transistor, wherein the second distance is greater than the first distance;
forming a stress liner layer covering the first and second transistors, the stress liner layer being capable of inducing stress on the first and second channel regions;
forming a dielectric layer over the stress liner layer;
forming first contact openings in communication with the first source/drain regions and second contact openings in communication with the second source/drain regions, the first and second contact openings extending through the dielectric layer and the stress layer; and
wherein at least a CA strap ratio or CA pitch associated with the first contact openings is selected to have a different value from at least a CA strap ratio or CA pitch associated with the second contact openings so as to mitigate differences in stress induced on the first and second channel regions by the stress liner layer.
2. The method as claimed in claim 1 , wherein at least the CA strap ratio or CA pitch associated with the first and second contact openings are selected so as to substantially match at least the Ion, Idsat, or Gmax of the first transistor with that for the second transistor.
3. The method as claimed in claim 1 , wherein the first and second transistors are both NFET.
4. The method as claimed in claim 3 , wherein the stress liner layer has a tensile stress and is capable of inducing a tensile stress on the first and second channel regions.
5. The method of claim 1 , wherein the first and second transistors are both PFET.
6. The method as claimed in claim 5 , wherein the stress liner layer has a compressive stress and is capable of inducing a compressive stress on the first and second channel regions.