Method to form thicker erase gate poly superflash NVM
View Patent ↗A method of forming a thick EG polysilicon over the FG and resulting device are provided. Embodiments include forming a CG on a substrate; forming an STI between a logic region and the CG; forming a polysilicon EG through the CG and CG HM; forming a polysilicon structure over the logic and STI; forming and overfilling with polysilicon a WL trench through the CG and CG HM, between the EG and STI; forming a buffer oxide in the polysilicon structure over the logic region and part of the STI; recessing the buffer oxide and etching back the polysilicon overfill down the CG HM; forming a second buffer oxide over the EG and logic region; recessing the WL polysilicon; removing the first and second buffer oxides; forming a mask with an opening over a center of the WL, the STI, and a majority of the logic region; and removing exposed polysilicon.
1. A method comprising:
forming a control gate (CG) and a CG hardmask (HM) on a substrate;
forming a shallow trench isolation (STI) region between a logic region and the CG;
forming a polysilicon erase gate (EG) through the CG and CG HM;
forming a polysilicon structure over the logic and STI regions;
forming and overfilling with polysilicon a word line (WL) trench through the CG and CG HM, between the EG and the STI region;
forming a first buffer oxide in the polysilicon structure over the logic region and part of the STI region;
recessing the first buffer oxide and etching back the polysilicon overfill down the CG HM;
forming a mask or second buffer oxide over the EG and logic region;
recessing the WL polysilicon;
removing the mask or second buffer oxide and the first buffer oxide;
forming a mask with an opening over a center of the WL, the STI region, and a majority of the logic region; and
removing exposed polysilicon.
2. A method according to claim 1 , further comprising:
forming a floating gate (FG) and interpoly dielectric (IPD) on the substrate prior to forming the CG and CG HM, wherein the FG and CG comprise polysilicon, the IPD comprises an oxide/nitride/oxide stack, and the CG HM comprises a nitride/oxide/nitride stack.
3. A method according to claim 2 , comprising forming the IPD of an oxide/nitride/oxide stack, and forming the CG HM of a nitride/oxide/nitride stack.
4. A method according to claim 1 , comprising forming the EG by:
forming a source region in the substrate by an N-type dopant implant;
oxidizing an upper portion of the source region;
forming nitride and oxide spacers on sidewalls of a trench; and
filling the trench with polysilicon.
5. A method according to claim 1 , further comprising forming nitride and oxide spacers on sidewalls of the WL trench prior to overfilling with polysilicon.
6. A method according to claim 1 , comprising:
forming the first buffer oxide to a thickness of 500 angstroms (Å) to 2000 Å.
7. A method according to claim 1 , comprising:
recessing the first buffer oxide by 250 Å to 1050 Å.
8. A method according to claim 1 , comprising recessing the WL polysilicon by 1200 Å to 1700 Å.
9. A method according to claim 1 , comprising removing exposed polysilicon in the WL trench by reactive ion etching (RIE).
10. A method according to claim 9 , comprising performing RIE in the WL trench.
11. A method according to claim 1 , comprising forming the mask over the logic region covering a portion of the polysilicon.
12. A method comprising:
forming a floating gate (FG) of polysilicon and interpoly dielectric (IPD) of an oxide/nitride/oxide stack on a substrate;
forming a control gate (CG) of polysilicon and a CG HM of nitride/oxide/nitride stack on the substrate;
forming a shallow trench isolation (STI) region between a logic region and the CG;
forming a polysilicon erase gate (EG) through the CG and CG HM;
forming a polysilicon structure over the logic and STI regions;
forming and overfilling with polysilicon a word line (WL) trench through the CG and CG HM, between the EG and the STI region;
forming a first buffer oxide to a thickness of 500 to 2000 angstroms (Å) in the polysilicon structure over the logic region and part of the STI region;
recessing the first buffer oxide by 250 to 1050 Å and etching back the polysilicon overfill down the CG HM;
forming a mask or second buffer oxide over the EG and logic region;
recessing the WL polysilicon to 1200 Å to 1700 Å;
removing the mask or second buffer oxide and the first buffer oxide;
forming a mask with an opening over a center of the WL, the STI region, and a majority of the logic region; and
removing exposed polysilicon by reactive ion etching (RIE).
13. A method according to claim 12 , comprising forming the EG by:
forming a source region in the substrate by an N-type dopant implant;
oxidizing an upper portion of the source region;
forming nitride and oxide spacers on sidewalls of a trench; and
filling the trench with polysilicon.
14. A method according to claim 12 , comprising forming nitride and oxide spacers on sidewalls of the WL trench prior to overfilling with polysilicon.