Hall element for 3-D sensing and method for producing the same
A method of forming a 3D Hall effect sensor and the resulting device are provided. Embodiments include forming a p-type well in a substrate; forming a first n-type well in a first region surrounded by the p-type well in top view; forming a second n-type well in a second region surrounding the p-type well; implanting n-type dopant in the first and second n-type wells; and implanting p-type dopant in the p-type well and the first n-type well.
1. A method comprising:
forming a p-type well in a substrate;
forming a first n-type well in a first region surrounded by the p-type well in top view;
forming a second n-type well in a second region surrounding the p-type well;
implanting an n-type dopant in the first n-type well and the second n-type well, respectively; and
implanting a p-type dopant in the p-type well and the first n-type well, respectively.
2. The method according to claim 1 , wherein the substrate comprises a p-type substrate.
3. The method according to claim 1 , comprising:
forming the second n-type well in the second region as a frame-shaped pattern in top view.
4. The method according to claim 1 , comprising:
forming the first n-type well in the first region as a cross-shaped pattern in top view.
5. The method according to claim 4 , comprising:
forming the p-type well to completely surround the cross-shaped n-type well.
6. The method according to claim 1 , further comprising:
forming shallow trench isolation regions prior to forming the p-type well.
7. The method according to claim 1 , comprising:
forming the first n-type well or the second n-type well prior to forming the p-type well.
8. The method according to claim 1 , comprising:
forming the first n-type well or the second n-type well after forming the p-type well.
9. The method according to claim 1 , comprising:
implanting the n-type dopant and the p-type dopant respectively before forming the first n-type well and the second n-type well and the p-type well.
10. The method according to claim 1 , comprising:
implanting the n-type dopant and p-type dopant respectively after forming the first n-type well and the second n-type well and the p-type well.
11. The method according to claim 1 , further comprising:
forming and patterning a nitride layer and to expose selected regions;
performing self-aligned silicidation in the selected regions to reduce resistance in each respective first n-type well, the second n-type well and the p-type well; and
forming an interlayer dielectric (ILD) over each respective first n-type well, the second n-type well and the p-type well.
12. The method according to claim 11 , further comprising:
forming contacts in the ILD; and
performing back-end-of-line (BEOL) processing.
13. A method comprising:
forming a p-type well in a p-type substrate;
forming a first n-type well in a first region surrounded by the p-type well in top view, the first region having a crossed-shaped pattern in top view;
forming a second n-type well in a second region surrounding the p-type well, the second region having a frame-shaped pattern in top view;
implanting an n-type dopant in the first n-type well and the second n-type well, respectively; and
implanting a p-type dopant in the p-type well and the first n-type well, respectively.
14. The method according to claim 13 , further comprising:
forming and patterning a nitride layer and to expose selected regions;
performing self-aligned silicidation in the selected regions to reduce resistance in the first n-type well, the second n-type well and the p-type well; and
forming an interlayer dielectric (ILD) over each of the first n-type well, the second n-type well and the p-type well;
forming contacts in the ILD; and
performing back-end-of-line (BEOL) processing.