EEPROM cell

1. A method of forming a device comprising:

providing a substrate prepared with a cell area;

forming first and second gates of first and second transistors in the cell area, wherein

the first gate includes a second sub-gate surrounding a first sub-gate, the first and second sub-gates of the first gate are separated by a first intergate dielectric layer, and

the second gate includes a second sub-gate surrounding a first sub-gate, the first and second sub-gates of the second gate are separated by a second intergate dielectric layer;

forming first and second junctions of the first and second transistors;

forming a first gate terminal coupled to the second sub-gate of the first transistor; and

forming a second gate terminal coupled to at least the first sub-gate of the second transistor.

2. The method of claim 1 comprises:

forming a first cell terminal coupled to the first junction of the first transistor; and

forming a second cell terminal coupled to the first junction of the second transistor.

3. The method of claim 2 wherein:

the first transistor serves as a control gate;

the second transistor serves as a select gate;

the first cell terminal is coupled to the first transistor serves as a bitline; and

the second gate terminal serves as a wordline.

4. The method of claim 1 wherein forming the second junctions of the first and second transistors comprises forming a common second junction of the first and second transistors.

5. The method of claim 1 wherein:

the first transistor serves as a control gate;

the second transistor serves as a select gate;

a first cell terminal coupled to the first transistor serves as a bitline; and

the second gate terminal serves as a wordline.

6. The method of claim 1 wherein forming the first and second gates comprises:

forming a first sub-gate layer on the substrate;

patterning the first sub-gate layer to form first sub-gates of the first and second gates;

forming a common intergate dielectric layer on the substrate covering the first sub-gates, the common intergate dielectric layer serves as the first and second intergate dielectric layers of the first and second gates;

forming a second sub-gate layer on the substrate over the common intergate dielectric layer; and

patterning the second sub-gate layer to form the first and second gates, wherein the second sub-gates of the first and second gates wrap around the first sub-gates of the first and second gates.

7. The method of claim 6 wherein:

the first and second junctions of the first and second transistors include a heavily doped portion and a lightly doped extension portion extending from the first gate to the second gate; and

comprises

forming the lightly doped extension portion of the first and second junctions after forming the first sub-gates of the first and second gates, and

forming the heavily doped portion of the first and second junctions after forming the second sub-gates of the first and second gates.

8. The method of claim 7 wherein the second sub-gate surrounding the first sub-gate of the first gate improves charge retention.

9. The method of claim 6 wherein patterning the second sub-gate layer also forms gates of other transistors in the device.

10. The method of claim 1 wherein the intergate dielectric layer comprises an oxide-nitride-oxide stack.

11. The method of claim 1 wherein the first intergate dielectric layer comprises multiple dielectric layers.

12. The method of claim 1 wherein the second gate terminal is coupled to the first and second sub-gates of the second gate.

13. The method of claim 1 wherein the second gate terminal is coupled to the first sub-gate of the second gate while the second sub-gate of the second gate is floated.

14. The method of claim 1 wherein the device comprises a ETOX device.

15. A method of forming a device comprising:

providing a cell having first and second transistors coupled in series, wherein the first and second transistors are disposed between first and second cell terminals, wherein

the first transistor includes a first gate with a second sub-gate surrounding a first sub-gate, the first and second sub-gates of the first gate are separated by a first intergate dielectric layer, and

the second transistor includes a second gate with a second sub-gate surrounding a first sub-gate, the first and second sub-gates of the second gate are separated by a second intergate dielectric layer;

coupling a first gate terminal to the second sub-gate of the first gate; and

coupling a second gate terminal to at least the first sub-gate of the second gate.

16. The method of claim 15 wherein the second sub-gate surrounding the first sub-gate of the first gate improves charge retention.

17. The method of claim 15 wherein:

the first transistor serves as a control gate;

the second transistor serves as a select gate;

the second gate terminal serves as a wordline; and comprises

coupling the first cell terminal to a first junction of the first transistor and serves as a bitline.

18. The method of claim 15 wherein the first intergate dielectric layer comprises multiple dielectric layers.

19. The method of claim 15 wherein the second gate terminal is coupled to the first and second sub-gates of the second gate.

20. The method of claim 15 wherein the second gate terminal is coupled to the first sub-gate of the second gate while the second sub-gate of the second gate is floated.

21. The method of claim 15 wherein the intergate dielectric layer comprises an oxide-nitride-oxide stack.