IP Library Granted Patent US 8,822,342
Granted Patent B2
US 8,822,342 · App. 12/981,519 · Granted Sep 2, 2014

Method to reduce depth delta between dense and wide features in dual damascene structures

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Quick Facts
Patent No.
US 8,822,342
App. No.
12/981,519
Granted
Sep 2, 2014
Kind
B2
Abstract

A method of forming a device is disclosed. The method includes providing a substrate prepared with a dielectric layer having first and second regions. The first region comprises wide features and the second region comprises narrow features. A depth delta exists between bottoms of the wide and narrow features. A non-conformal layer is formed on the substrate and it lines the wide and narrow trenches in the first and second regions. The non-conformal layer is removed. Removing the non-conformal layer reduces the depth delta between the bottoms of the wide and narrow features in the first and second region.

Claims (51)

1. A method of forming a device comprising:

providing a substrate prepared with a dielectric layer where interconnects are to be formed,

the dielectric layer comprising

trenches for lines and

vias for contacts,

the trenches being above the vias,

the dielectric layer having first and second regions,

wherein the first region comprises wide trenches and the second region comprises narrow trenches, and

wherein a depth delta exists between bottoms of the wide and narrow trenches;

forming a non-conformal layer on the substrate,

the non-conformal layer lining the wide and narrow trenches in the first and second regions;

etching the non-conformal layer in the wide and narrow trenches

to expose areas of the dielectric layer in the narrow trenches and

to remove the non-conformal layer from the bottom of the vias

while leaving an remaining amount of the non-conformal layer over the wide trenches; and

reducing the depth delta between the bottoms of the wide and narrow trenches in the first and second regions

by etching the remaining amount of the non-conformal layer and the dielectric layer,

the non-conformal layer having a lower etch rate than the dielectric layer, thereby allowing the narrow trenches to be etched further and faster than the wide trenches.

2. The method of claim 1 wherein a depth of the wide trenches in the first region is deeper than a depth of the narrow trenches in the second region.

3. The method of claim 2 wherein a percentage of the depth delta between the wide and narrow trenches is reduced by at least about 20-50%.

4. The method of claim 3 wherein forming the non-conformal layer comprises forming a non-conformal oxide layer.

5. The method of claim 1 wherein a percentage of the depth delta between the wide and narrow trenches is reduced by at least about 20-50%.

6. The method of claim 5 wherein forming the non-conformal layer comprises forming a non-conformal oxide layer.

7. The method of claim 1 wherein forming the non-conformal layer comprises forming a non-conformal oxide layer.

8. The method of claim 1

wherein removing the non-conformal layer exposes contact regions for communication with the interconnects to be formed within the vias.

9. The method of claim 8

wherein the contact regions for communication with the interconnects to be formed within the vias comprise lower interconnects.

10. The method of claim 1 wherein the non-conformal layer comprises silicon oxide or a low temperature oxide.

11. The method of claim 1 wherein thickness of the non-conformal layer in the first region is greater than in the second region.

12. A method of forming a device comprising:

providing a substrate prepared with a dielectric layer having first and second regions,

wherein the first region comprises wide dual damascene features and the second region comprises narrow dual damascene features,

the dual damascene features comprising trenches for lines and vias for contacts, the vias being below the trenches,

wherein a depth delta exists between bottoms of wide and narrow trenches;

forming a non-conformal layer on the substrate,

the non-conformal layer lining the wide and narrow dual damascene features in the first and second regions; and

etching the non-conformal layer in the wide and narrow trenches

to expose areas of the dielectric layer in the narrow trenches and

to remove the non-conformal layer from the bottom of the vias

while leaving a remaining amount of the non-conformal layer over the wide trenches; and

reducing the depth delta between the bottoms of the wide and narrow trenches in the first and second regions

by etching the remaining amount of the non-conformal layer and the dielectric layer,

the non-conformal layer having a lower etch rate than the dielectric layer, thereby allowing the narrow trenches to be etched further and faster than the wide trenches.

13. The method of claim 12 wherein a depth of the wide trenches in the first region is deeper than a depth of the narrow trenches in the second region.

14. The method of claim 13 wherein a percentage of the depth delta between the wide and narrow trenches is reduced by at least about 20-50%.

15. The method of claim 12 wherein forming the non-conformal layer comprises forming a non-conformal oxide layer.

16. The method of claim 15 wherein a percentage of the depth delta between the wide and narrow trenches is reduced by at least about 20-50%.

17. The method of claim 12 wherein the thickness of the non-conformal layer

in the narrow trench is about 40-60% less than the thickness in the wide trench.

18. The method of claim 17 wherein removing the non-conformal layer further comprises performing a cleaning process after performing the etch to remove the remaining non-conformal layer.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 19, 2020
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
Reel/Frame 054481/0673 →
SECURITY AGREEMENT Recorded Nov 27, 2018
From: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
To: WILMINGTON TRUST, NATIONAL ASSOCIATION
Reel/Frame 047660/0203 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 22, 2011
From: PALLACHALIL, MUHAMMED SHAFI KURIKKA VALAPPIL
To: INFINEON TECHNOLOGIES NORTH AMERICA CORP.
Reel/Frame 025845/0081 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 22, 2011
From: MIYAJIMA, HIDESHI
To: TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
Reel/Frame 025844/0895 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 22, 2011
From: OGUNSOLA, OLUWAFEMI. O.; HICHRI, HABIB; ANGYAL, MATTHEW
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 025846/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 22, 2011
From: SRIVASTAVA, RAVI PRAKASH
To: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
Reel/Frame 025845/0942 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 22, 2011
From: CHILD, CRAIG
To: ADVANCED MICRO DEVICES CORPORATION
Reel/Frame 025845/0017 →