Latch-up immunity nLDMOS
View Patent ↗An improved nLDMOS ESD protection device having an increased holding voltage is disclosed. Embodiments include: providing in a substrate a DVNW region; providing a HVPW region in the DVNW region; providing bulk and source regions in the HVPW region; providing a drain region in the DVNW region, separate from the HVPW region; and providing a polysilicon gate over a portion of the HVPW region and the DVNW region.
1. A device comprising:
a substrate;
a dual voltage n-well (DVNW) region in the substrate;
a high voltage p-well (HVPW) region in the DVNW region;
bulk and source regions in the HVPW region;
a drain region in the DVNW region, separate from the HVPW region;
a polysilicon gate over a portion of the HVPW region and the DVNW region;
an n-well (NW) region in the DVNW region in the drain region, the NW region comprising a first N+ region;
second and third N+ regions in the HVPW region; and
a first P+ region separating the second and third N+ regions.
2. The device according to claim 1 , further comprising:
the device having no high voltage n-type double diffusion drain (HVNDDD) region.
3. The device according to claim 1 , comprising:
a silicided block layer on the first N+ region, a portion of the polysilicon gate, and the DVNW region therebetween.
4. The device according to claim 1 , wherein the second and third N+ regions and polysilicon gate being coupled to a ground rail.
5. The device according to claim 4 , wherein the first N+ region is coupled to an I/O pad.
6. The device according to claim 5 , further comprising:
a second P+ region in the substrate, separate from the DVNW region, the second P+ region being coupled to the ground rail.
7. A device, comprising:
a p-type substrate;
a first P+ region in the p-type substrate;
a dual voltage n-well (DVNW) region in the p-type substrate, separate from the first P+ region;
a first N+ region in the DVNW region;
a first shallow trench isolation (STI) layer separating the first P+ region from the first N+ region;
a high voltage p-well (HVPW) region in the DVNW region, separate from the first N+ region;
a second and third N+ region in the HVPW region;
a second STI layer separating the first and second N+ regions;
a second P+ region in the HVPW region separating the second and third N+ regions;
a polysilicon gate on a portion of the HVPW region and on the DVNW region;
a fourth N+ region in the DVNW region; and
a silicided block layer on a portion of the polysilicon gate, the fourth N+ region, and the DVNW region therebetween;
the first P+ region and second and third N+ regions being coupled to a ground rail, and the fourth N+ region being coupled to an I/O pad.
8. The device according to claim 7 , comprising:
an n-well (NW) region in the DVNW region, the fourth N+ region being in the NW region.
9. The device according to claim 8 , comprising:
a third STI region in the DVNW region, between the fourth N+ region and the HVPW region, the polysilicon gate and silicided block layer overlying the third STI region.
10. The device according to claim 9 , further comprising:
the device having no high voltage n-type double diffusion drain (HVNDDD) region.
11. A device comprising:
a dual voltage n-well (DVNW) region in a substrate;
a high voltage p-well (HVPW) region in the DVNW region;
bulk and source regions in the HVPW region;
a drain region in the DVNW region, separate from the HVPW region;
a polysilicon gate over a portion of the HVPW region and the DVNW region;
a first N+ region in an n-well (NW) region in the DVNW region in the drain region; and
in the source region in the HVPW region, second and third N+ regions and a first P+ region, the second and third N+ regions being separated by the first P+ region,
wherein the second and third N+ regions and the polysilicon gate are coupled to a ground rail.
12. The device according to claim 11 , comprising:
a silicided block layer on the first N+ region, a portion of the polysilicon gate, and the DVNW therebetween.
13. The device according to claim 11 , wherein the first N+ region is coupled to an I/O pad.
14. The device according to claim 11 , further comprising:
a second P+ region in the substrate, separate from the DVNW region.
15. The device according to claim 14 , wherein the second P+ region is coupled to the ground rail.
16. The device according to claim 15 , wherein
an ESD current path is created from the I/O pad to the ground rail through the NW, DVNW, HVPW, and third N+ regions during an ESD event.