Integrated circuit system with ultra-low k dielectric and method of manufacture thereof
View Patent ↗A method of manufacturing an integrated circuit system includes: providing a etch stop layer; forming a layer stack over the etch stop layer with the layer stack having an anti-reflective coating layer over a low temperature oxide layer; forming a photoresist layer over the anti-reflective coating layer; forming a first resist line and a second resist line from the photoresist layer with the first resist line and the second resist line separated by a through line pitch on the anti-reflective coating layer; etching the anti-reflective coating layer using a low-pressure polymer burst with a non-oxidizing gas mixture to remove a portion of the anti-reflective coating layer; and forming a first polymer layer over the first resist line.
1. An integrated circuit system comprising:
an etch stop layer;
a layer stack having an anti-reflective coating layer over a low temperature oxide layer;
a photoresist layer over the anti-reflective coating layer;
a first resist line and a second resist line etched from the photoresist layer with the first resist line and the second resist line separated by a through line pitch on the anti-reflective coating layer;
the anti-reflective coating layer etched using a low-pressure polymer burst with a non-oxidizing gas mixture to remove a portion of the anti-reflective coating layer; and
a first polymer layer over the first resist line.
2. The system as claimed in claim 1 wherein the low-pressure polymer burst has a polymer burst pressure of between 10 mTorr and 50 mTorr.
3. The system as claimed in claim 1 wherein the low-pressure polymer burst has a polymer burst exposure time of between 2 seconds and 10 seconds.
4. The system as claimed in claim 1 further comprising a passivation layer on the side of the first resist line.
5. The system as claimed in claim 1 wherein the layer stack includes:
an ultra-low k dielectric layer over a portion of the etch stop layer;
a hardmask layer over the ultra-low k layer;
a planarizing layer over the hardmask layer; and
the low temperature oxide layer over the planarizing layer.
6. The system as claimed in claim 1 further comprising a second polymer layer formed over the second resist line for reducing the critical dimension of a first polymer opening while keeping the through line pitch the same.
7. The system as claimed in claim 1 wherein the non-oxidizing gas mixture comprises N2 and H2 with more H2 than N2.
8. The system as claimed in claim 1 wherein the non-oxidizing gas mixture comprises CHF3, CH3F, or C4F8.
9. The system as claimed in claim 1 wherein the non-oxidizing gas mixture comprises CH2F2.
10. The system as claimed in claim 1 wherein the photoresist layer includes the photoresist layer etched with a reactive ion etching process.
11. A method of manufacture of an integrated circuit system comprising:
providing an etch stop layer;
forming a layer stack over the etch stop layer with the layer stack having an anti-reflective coating layer over a low temperature oxide layer;
forming a photoresist layer over the anti-reflective coating layer;
forming a first resist line and a second resist line from the photoresist layer with the first resist line and the second resist line separated by a through line pitch on the anti-reflective coating layer;
etching the anti-reflective coating layer using a low-pressure polymer burst with a non-oxidizing gas mixture to remove a portion of the anti-reflective coating layer; and
forming a first polymer layer over the first resist line.
12. The method as claimed in claim 11 wherein etching the anti-reflective coating layer includes using the low-pressure polymer burst with a polymer burst pressure of between 10 mTorr and 30 mTorr.
13. The method as claimed in claim 11 wherein etching the anti-reflective coating layer includes using the low-pressure polymer burst with a polymer burst exposure time of between 2 seconds and 10 seconds.
14. The method as claimed in claim 11 further comprising forming a passivation layer on the side of the first resist line.
15. The method as claimed in claim 11 wherein forming the layer stack includes:
forming an ultra-low k dielectric layer over a portion of the etch stop layer;
forming a hardmask layer over the ultra-low k layer;
forming a planarizing layer over the hardmask layer; and
forming the low temperature oxide layer over the planarizing layer.
16. A method of manufacture of an integrated circuit system comprising:
providing an etch stop layer;
forming a layer stack over the etch stop layer with the layer stack having an anti-reflective coating layer over a low temperature oxide layer;
forming a photoresist layer over the anti-reflective coating layer;
forming a first resist line and a second resist line from the photoresist layer with the first resist line and the second resist line separated by a through line pitch on the anti-reflective coating layer;
etching the anti-reflective coating layer using a low-pressure polymer burst with a non-oxidizing gas mixture to remove a portion of the anti-reflective coating layer; and
forming a first polymer layer over the first resist line; and
forming a second polymer layer over the second resist line for reducing the critical dimension of a first polymer opening while keeping the through line pitch the same.
17. The method as claimed in claim 16 wherein etching the anti-reflective coating layer includes using the non-oxidizing gas mixture comprises N2 and H2 with more N2 than H2.
18. The method as claimed in claim 16 wherein etching the anti-reflective coating layer includes using the non-oxidizing gas mixture comprises H2.
19. The method as claimed in claim 16 wherein etching the anti-reflective coating layer includes using the non-oxidizing gas mixture comprises CH2F2.
20. The method as claimed in claim 16 wherein etching the photoresist layer includes etching the photoresist layer with a reactive ion etching process.