Integrated circuit system employing resistance altering techniques

1. A method of manufacture of an integrated circuit system comprising:

providing a substrate including a first region and a second region;

forming a first device over the first region, the first device having a first gate over a first gate dielectric;

forming a resistance device over the second region, the resistance device having a second gate over a second gate dielectric similar to the first gate and the first gate dielectric of the first device;

forming a first dielectric layer and a second dielectric layer over the substrate wherein forming the second dielectric layer includes increasing the density of the second dielectric layer to increase a resistance value of the resistance device;

removing a portion of the second dielectric layer; and

annealing the integrated circuit system to remove dopant from the resistance device.

2. The method as claimed in claim 1 wherein:

forming the first dielectric layer includes forming an oxide and forming the second dielectric layer includes forming a nitride.

3. The method as claimed in claim 1 wherein:

removing a portion of the second dielectric layer includes removing the second dielectric layer from over the first device.

4. The method as claimed in claim 1 wherein:

annealing the integrated circuit system includes forming the resistance device with a sheet resistance value between about 700 ohms/square to about 900 ohms/square.

5. The method as claimed in claim 1 wherein:

increasing the density of the second dielectric layer includes forming the second dielectric layer by rapid thermal chemical vapor deposition.

6. A method of manufacture of an integrated circuit system comprising:

providing a substrate including a first region and a second region;

forming a first device over the first region, the first device having a first gate over a first gate dielectric;

forming a resistance device over the second region, the resistance device having a second gate over a second gate dielectric similar to the first gate and the first gate dielectric of the first device;

forming a first dielectric layer over the substrate;

processing the first dielectric layer with a hydrogen treatment;

forming a second dielectric layer over the first dielectric layer wherein forming the second dielectric layer includes increasing the density of the second dielectric layer to increase a resistance value of the resistance device;

removing a portion of the second dielectric layer; and

annealing the integrated circuit system to remove dopant from the resistance device.

7. The method as claimed in claim 6 wherein:

processing the first dielectric layer with a hydrogen treatment includes utilizing a hydrogen forming gas anneal.

8. The method as claimed in claim 6 wherein:

processing the first dielectric layer with a hydrogen treatment includes utilizing a hydrogen plasma treatment.

9. The method as claimed in claim 6 wherein:

forming the second dielectric layer over the first dielectric layer prevents deposition of an electrical contact over the resistance device.

10. The method as claimed in claim 6 wherein:

increasing the density of the second dielectric layer includes forming the second dielectric layer by rapid thermal chemical vapor deposition.

11. A method of manufacture of an integrated circuit system comprising:

providing a substrate including a first region and a second region;

forming a first device and a second device over the first region, the first device having a first gate over a first gate dielectric;

forming a resistance device over the second region, the resistance device having a second gate over a second gate dielectric similar to the first gate and the first gate dielectric of the first device;

forming a first dielectric layer and a second dielectric layer over the substrate wherein forming the second dielectric layer includes increasing the density of the second dielectric layer to increase a resistance value of the resistance device;

removing a portion of the second dielectric layer; and

annealing the integrated circuit system to remove dopant from the resistance device.

12. The method as claimed in claim 11 wherein:

forming the first dielectric layer includes forming an oxide and forming the second dielectric layer includes forming a nitride.

13. The method as claimed in claim 11 wherein:

removing a portion of the second dielectric layer includes removing the second dielectric layer from over the first region.

14. The method as claimed in claim 11 wherein:

removing a portion of the second dielectric layer includes removing the second dielectric layer from over the second device or removing the second dielectric layer from over the first device and the second device.

15. The method as claimed in claim 11 wherein:

removing a portion of the second dielectric layer includes removing the second dielectric layer from over the first region either before annealing or after annealing.

16. The method as claimed in claim 11 wherein:

annealing the integrated circuit system includes a stress memorization transfer process.

17. The method as claimed in claim 11 wherein:

providing the substrate includes providing the substrate with a crystalline plane that is rotated about forty-five degrees.

18. The method as claimed in claim 11 further comprising:

processing the first dielectric layer with a hydrogen treatment.

19. The method as claimed in claim 11 wherein:

increasing the density of the second dielectric layer includes forming the second dielectric layer by rapid thermal chemical vapor deposition.

20. The method as claimed in claim 11 further comprising:

forming an electrical contact over the first gate and a source/drain of the first device and the second device.