Low voltage semiconductor memory device and method of operation
View Patent ↗A semiconductor device for storing data includes a memory cell. The memory cell comprises a plurality of transistors. A trimmable sense amplifier is electrically connected to the memory cell. The trimmable sense amplifier is configured to provide variable current to said memory cell. A charge pump is also electrically connected to the memory cell. The charge pump includes a plurality of diodes disposed in series with one another. The charge pump includes an input for receiving an input voltage and an output for providing an output voltage greater than the input voltage to the memory cell.
1. A semiconductor device, comprising: a memory cell including a plurality of transistors;
a trimmable sense amplifier electrically connected to said memory cell configured to provide variable current to said memory cell, wherein said trimmable sense amplifier comprises:
a reference current source;
a first current mirror including a first transistor and a plurality of second transistors, and
a plurality of switches electrically connected to said plurality of second transistors for connecting and disconnecting at least one of said second transistors.
2. The semiconductor device as set forth in claim 1 , wherein the variable current varies between about two microamperes (“μA”) and nine μA.
3. The semiconductor device as set forth in claim 1 , further comprising a buffer amplifier electrically connected to said memory cell and said trimmable sense amplifier.
4. The semiconductor device as set forth in claim 1 , wherein said memory cell comprises an electrically erasable programmable read-only memory (“EEPROM”) cell.
5. The semiconductor device as set forth in claim 1 further comprising a controller in communication with said trimmable sense amplifier for controlling the current provided to said memory cell.
6. The semiconductor device as set forth in claim 1 , further comprising a second current mirror including a third transistor electrically connected to said plurality of second transistors and a fourth transistor electrically connected to said memory cell.
7. A semiconductor device, comprising:
a memory cell including a plurality of transistors; and
a charge pump electrically connected to said memory cell,
a trimmable sense amplifier electrically connected to said memory cell configured to provide variable current to said memory cell, and
said charge pump including an input for receiving an input voltage and an output for providing an output voltage greater than the input voltage to said memory cell.
8. The semiconductor device as set forth in claim 7 , wherein said trimmable sense amplifier comprises:
a reference current source; and
a first current mirror including a first transistor and a plurality of second transistors.
9. The semiconductor device as set forth in claim 8 , wherein said trimmable sense amplifier further comprising a plurality of switches electrically connected to said plurality of second transistors for connecting and disconnecting at least one of said second transistors.
10. The semiconductor device as set forth in claim 9 , further comprising a second current mirror including a third transistor electrically connected to said plurality of second transistors and a fourth transistor electrically connected to said memory cell.
11. The semiconductor device as set forth in claim 7 , wherein said charge pump includes a plurality of diodes disposed in series with one another.
12. The semiconductor device as set forth in claim 11 , wherein each diode is a Schottky diode.
13. The semiconductor device as set forth in claim 11 , wherein said plurality of diodes comprises at least twenty-five diodes.
14. The semiconductor device as set forth in claim 7 , wherein said charge pump provides an output voltage greater than 13 times the input voltage.
15. The semiconductor device as set forth in claim 14 , wherein said charge pump provides an output voltage of about 20 V from the input voltage of about 1.5 V.
16. The semiconductor device as set forth in claim 7 , wherein said charge pump comprises a charge pump oscillator configured to generate an oscillating signal.
17. The semiconductor device as set forth in claim 16 , wherein said charge pump comprises a phase splitter electrically coupled to said charge pump oscillator and said plurality of diodes and configured to receive the oscillating signal and split the oscillating signal into a first clock signal and a second clock signal.
18. The semiconductor device as set forth in claim 17 , wherein said charge pump comprises at least one frequency divider electrically coupled between said charge pump oscillator and said phase splitter.
19. The semiconductor device as set forth in claim 7 , wherein said memory cell comprises an electrically erasable programmable read-only memory (“EEPROM”) cell.
20. A method of operating a semiconductor device, the semiconductor device including a memory cell, said method comprising:
providing a variable current to the memory cell from a trimmable sense amplifier;
receiving an input voltage at an input of a charge pump; generating an output voltage greater than the input voltage with the charge pump; and
providing the output voltage from the charge pump to the memory cell.