Integrated circuit system with high voltage transistor and method of manufacture thereof

1. A method of manufacture of an integrated circuit system comprising:

providing a semiconductor substrate having an active region, implanted with impurities of a first type at a first concentration;

forming an isolation region around the active region;

forming a parasitic transistor by applying a gate electrode, implanted with impurities of a second type at a second concentration, over the active region and the isolation region; and

applying an isolation edge implant, with the impurities of the first type at a third concentration that is greater than or equal to the second concentration, for suppressing the parasitic transistor.

2. The method as claimed in claim 1 further comprising forming an opening in the gate electrode for applying the isolation edge implant.

3. The method as claimed in claim 1 further comprising forming a source and a drain on opposite sides of the gate electrode.

4. The method as claimed in claim 1 further comprising forming a channel under the gate electrode.

5. The method as claimed in claim 1 wherein applying the isolation edge implant includes implanting a square, a rectangle, a circle, or a triangle.

6. A method of manufacture of an integrated circuit system comprising:

providing a semiconductor substrate having an active region, implanted with impurities of a first type at a first concentration;

forming an isolation region around the active region including forming a shallow trench isolation;

forming a parasitic transistor by applying a gate electrode, implanted with impurities of a second type at a second concentration, over the active region and the isolation region including applying a layer of poly-silicon on a gate oxide layer; and

applying an isolation edge implant, with the impurities of the first type at a third concentration that is greater than or equal to the second concentration, for suppressing the parasitic transistor including increasing a threshold voltage of the parasitic transistor.

7. The method as claimed in claim 6 further comprising forming an opening in the gate electrode for applying the isolation edge implant in which forming the opening includes etching the opening to a 0.3 μm by 0.3 μm dimension.

8. The method as claimed in claim 6 further comprising forming a source and a drain on opposite sides of the gate electrode including implanting impurities of a second type at greater than or equal to the first concentration under the source and the drain.

9. The method as claimed in claim 6 further comprising forming a channel under the gate electrode including forming a high voltage metal oxide semiconductor channel, a double-diffused drain metal oxide semiconductor channel, a linear diffused metal oxide semiconductor channel, a vertical double-diffused metal oxide semiconductor channel, a low voltage metal oxide semiconductor channel, or a combination thereof on the semiconductor substrate.

10. The method as claimed in claim 6 wherein applying the isolation edge implant includes implanting a square, a rectangle, a circle, or a triangle including positioning an implant shape within the gate electrode and on the edge of the active region.

11. An integrated circuit system comprising:

a semiconductor substrate having an active region, implanted with impurities of a first type at a first concentration;

an isolation region around the active region;

a parasitic transistor formed by a gate electrode, implanted with impurities of a second type at a second concentration, over the active region and the isolation region; and

an isolation edge implant, with the impurities of the first type at a third concentration that is greater than or equal to the second concentration, for suppressing the parasitic transistor.

12. The system as claimed in claim 11 wherein the gate electrode having an opening with the isolation edge implant applied therethrough.

13. The system as claimed in claim 11 further comprising a source and a drain on opposite sides of the gate electrode.

14. The system as claimed in claim 11 further comprising a channel under the gate electrode.

15. The system as claimed in claim 11 wherein the isolation edge implant includes a square, a rectangle, a circle, or a triangle implanted.

16. The system as claimed in claim 11 further comprising:

a shallow trench isolation formed around the active region; and

a layer of poly-silicon on a gate oxide layer is the gate electrode.

17. The system as claimed in claim 16 wherein the gate electrode having an opening with the isolation edge implant applied therethrough includes a 0.3 μm by 0.3 μm opening in the gate electrode.

18. The system as claimed in claim 16 further comprising a source and a drain on opposite sides of the gate electrode includes impurities of a second type at greater than or equal to the first concentration implanted under the source and the drain.

19. The system as claimed in claim 16 further comprising a channel under the gate electrode includes a high voltage metal oxide semiconductor channel, a double-diffused drain metal oxide semiconductor channel, a linear diffused metal oxide semiconductor channel, a vertical double-diffused metal oxide semiconductor channel, a low voltage metal oxide semiconductor channel, or a combination thereof on the semiconductor substrate.

20. The system as claimed in claim 16 wherein the isolation edge implant includes a square, a rectangle, a circle, or a triangle implanted includes an implant shape within the gate electrode and on the edge of the active region.