Reliable non-volatile memory device

1. A method for forming a device comprising:

providing a substrate prepared with a memory cell region; and

forming at least first and second memory cells on the memory cell region, wherein forming each of the memory cells comprises

forming a split gate having first and second gates, wherein the first gate is a storage gate having a control gate over a floating gate and the second gate is a wordline, wherein forming the split gate comprises forming a floating gate dielectric over and in direct contact with the substrate,

forming re-oxidized layers which extend from top to bottom of the control gate on sidewalls of the control gate,

forming control gate spacers on the sidewalls of the control gate,

forming sacrificial spacers on and in direct contact with the control gate spacers,

removing the sacrificial spacer which is formed on the control gate spacer on a second gate side of the control gate,

forming floating gate spacers on sides of the first gate, wherein the floating gate spacer formed on a second gate side of the first gate is in direct contact with the control gate spacer while the floating gate spacer formed on a first or an erase gate side of the first gate is in direct contact with the sacrificial spacer,

forming a first source/drain (S/D) region adjacent to the second gate and a second S/D region adjacent to the first gate, wherein the first and second gates are coupled in series and the second S/D region being a common S/D region for adjacent first and second memory cells,

forming a tunneling oxide layer which lines at least sidewalls of the first gates adjacent to the common S/D region and over a top surface of the common S/D region,

forming an erase gate dielectric over the tunneling oxide layer and over the top surface of the common S/D region, and

forming an erase gate over the common S/D region, wherein the erase gate is isolated from the common S/D region by the erase gate dielectric, a portion of the tunneling oxide layer and a portion of the floating gate dielectric over the top surface of the common S/D region, wherein a top surface of the erase gate dielectric is below a top surface of the floating gate.

2. The method of claim 1 wherein forming the split gate comprises:

forming a floating gate electrode layer over the floating gate dielectric layer;

forming a storage gate dielectric layer over the floating gate electrode layer;

forming a control gate electrode layer over the storage gate dielectric layer; and

forming a hard mask layer over the control gate electrode layer.

3. The method of claim 2 wherein forming the split gate comprises:

patterning the hard mask and control gate electrode layers to form the control gate by an etch process, wherein the etch is highly selective to material of the control gate and stops at top surface of the storage gate dielectric layer.

4. The method of claim 3 wherein:

the storage gate dielectric layer comprises an oxide-nitride-oxide (ONO) stack;

the control gate electrode layer comprises polysilicon; and

the etch process is highly selective to the polysilicon material of the control gate electrode layer and the etch process stops at nitride layer of the ONO stack.

5. The method of claim 3 wherein the re-oxidized layers are formed after patterning the hard mask and control gate electrode layers and the re-oxidized layers are aligned with sides of the patterned hard mask layer.

6. The method of claim 3 comprising forming the control gate spacers over and in direct contact with sides of the patterned hard mask and re-oxidized layers, wherein the control gate spacers comprise a top surface which is coplanar with a top surface of the hard mask and a bottom surface which is coplanar with a bottom surface of the control gate.

7. The method of claim 6 wherein the control gate spacers comprise nitride spacers.

8. The method of claim 6 comprising:

forming the sacrificial spacers on and in direct contact with the sidewalls of the control gate spacers; and

performing a gate threshold voltage (Vt) adjustment implant in regions of the substrate where second gates are to be formed.

9. The method of claim 8 wherein forming the split gate comprises patterning the storage gate dielectric and floating gate electrode layers after performing the Vt adjustment implant, wherein the storage gate dielectric and floating gate electrode on the second sidewall of the storage gate are aligned with the control gate spacer while the storage gate dielectric and floating gate electrode on the first sidewall of the storage gate extend beyond the control gate spacer, wherein the tunneling oxide layer is disposed over and in direct contact with a portion of the erase gate side of the storage gate dielectric.

10. A method for forming a device comprising:

providing a substrate prepared with a memory cell region; and

forming at least first and second memory cells on the memory cell region, wherein forming each of the memory cells comprises

forming a split gate having first and second gates, wherein the first gate is a storage gate having a control gate over a floating gate and the second gate is a wordline, wherein forming the split gate comprises forming a floating gate dielectric over and in direct contact with the substrate,

forming re-oxidized layers which extend from top to bottom of the control gate on sidewalls of the control gate,

forming control gate spacers on the sidewalls of the control gate,

forming sacrificial spacers on and in direct contact with sidewalls of the control gate spacers,

removing the sacrificial spacer which is formed on the control gate spacer on a second gate side of the control gate,

forming floating gate spacers on sides of the first gate, wherein the floating gate spacer formed on a second gate side of the first gate is in direct contact with the control gate spacer while the floating gate spacer formed on a first or an erase gate side of the first gate is in direct contact with the sacrificial spacer,

forming a first source/drain (S/D) region adjacent to the second gate and a second S/D region adjacent to the first gate, wherein the first and second gates are coupled in series and the second S/D region being a common S/D region for adjacent first and second memory cells,

forming a tunneling oxide layer which lines at least sidewalls of the first gates adjacent to the common S/D region and over a top surface of the common S/D region,

forming an erase gate dielectric over the tunneling oxide layer and over the top surface of the common S/D region, and

forming an erase gate over the common S/D region, wherein the erase gate is isolated from the common S/D region by the erase gate dielectric, a portion of the tunneling oxide layer and a portion of the floating gate dielectric over the top surface of the common S/D region.

11. The method of claim 10 wherein the floating gate spacers comprise high temperature oxide spacers.

12. The method of claim 10 wherein the common S/D region adjacent to the first gates of adjacent first and second memory cells is a buried source line (SL) which is formed by performing an implant process to implant first polarity type dopants in region of the substrate between the first gates of adjacent first and second memory cells, wherein the buried SL comprises a top surface which is coplanar with a top surface of the substrate.

13. The method of claim 12 comprising:

removing floating gate spacers which are formed on sidewalls of the first gates adjacent to the buried SL; and wherein

forming the tunneling oxide layer which lines sidewalls of the first gates adjacent to the buried SL and the top surface of the buried SL is performed after removing the floating gate spacers.

14. The method of claim 1 wherein the second gate and erase gate are formed simultaneously.