IP Library Granted Patent US 7,998,831
Granted Patent B2
US 7,998,831 · App. 12/062,534 · Granted Aug 16, 2011

Planarized passivation layer for semiconductor devices

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Quick Facts
Patent No.
US 7,998,831
App. No.
12/062,534
Granted
Aug 16, 2011
Kind
B2
Abstract

A semiconductor device includes a substrate having a dielectric layer and a device layer on the substrate. The device layer has an opening. First and second sublayers are disposed on the device layer and line the opening. The second sublayer serves as a stop layer for planarization to provide a substantially planarized top surface for the semiconductor device.

Claims (65)

1. A method of fabricating a semiconductor device comprising:

providing a substrate having a dielectric layer and a device layer formed thereon, the device layer is on top of the dielectric layer, the device layer having a top surface;

forming an opening through the device layer;

forming first and second sublayers on the device layer and lining the opening;

depositing a fill layer to fill the opening;

removing excess fill material of the fill layer, wherein removing the excess fill material includes removing portions of the second sublayer over the top surface, to expose the first sublayer over the top surface of the device layer to form a substantially planar top surface of the semiconductor device.

2. The method of claim 1 wherein the device layer comprises a reflective layer.

3. The method of claim 2 wherein the reflective layer comprises a conductive material.

4. The method of claim 1 wherein the first sublayer comprises oxide and the second sublayer comprises nitride.

5. The method of claim 1 wherein the first sublayer serves as a passivation layer to protect the device layer.

6. The method of claim 1 wherein the fill layer comprises a dielectric material.

7. The method of claim 1 wherein removing the fill layer is achieved using chemical mechanical polishing.

8. The method of claim 1 further comprising depositing liquid crystal materials on top of the second sublayer and fill layer.

9. The method of claim 1 further comprising removing the second sublayer on top of the device layer.

10. The method of claim 1 further comprising forming a surface passivation layer on the surface of the substrate, covering the first, second sublayers and the fill.

11. A method of fabricating a semiconductor device comprising:

providing a substrate comprising

a base substrate with a dielectric layer formed thereon,

a device layer on top of the dielectric layer, and

first and second sublayers on top of the device layer;

forming an opening through the second sublayer;

providing a fill layer on top of the second sublayer and fill the opening;

planarizing the fill layer until it reaches a top surface of the second sublayer, the second sublayer serves as a stop layer such that a substantially planarized top surface is formed for the semiconductor device.

12. The method of claim 11 further comprising removing the second sublayer to expose top surface of the first sublayer.

13. The method of claim 12 further comprising forming a surface passivation layer to cover the first sublayer and the fill layer.

14. The method of claim 11 further comprising forming a surface passivation liner on the surface of the substrate, covering the second sublayer and the fill.

15. The method of claim 11 wherein:

the device layer comprises a reflective layer;

the first sublayer comprises a first dielectric material; and

the second sublayer comprises a second dielectric material.

16. The method of claim 15 wherein the reflective layer comprises a conductive material.

17. The method of claim 15 wherein the reflective layer comprises a conductive material selected from Al, AlCuSi or AlCu.

18. The method of claim 15 wherein the second dielectric material can be removed selective to the first dielectric material.

19. The method of claim 15 wherein:

the first dielectric material comprises silicon oxide; and

the second dielectric material comprises silicon nitride.

20. The method of claim 11 comprises further processing to form a liquid crystal device.

21. A method of fabricating a semiconductor device comprising:

providing a substrate prepared with a device layer, first and second sublayers on the device layer and an opening in the device layer, the device layer having a top surface;

depositing a fill material to form a fill layer, the fill material filling the opening;

removing excess fill material of the fill layer, wherein removing the excess fill material includes removing portions of the second sublayer over the top surface, to expose the first sublayer over the top surface of the device layer to form a substantially planar top surface of the semiconductor device.

22. The method of claim 21 wherein the first and second sublayers are formed on the device layer with the opening, the first and second sublayers are disposed on the device layer and line the opening.

23. The method of claim 22 wherein:

the device layer comprises a reflective layer;

the first sublayer comprises a first dielectric material; and

the second sublayer comprises a second dielectric material.

24. The method of claim 23 wherein the reflective layer comprises a conductive material.

25. The method of claim 23 wherein the reflective layer comprises a conductive material selected from Al, AlCuSi or AlCu.

26. The method of claim 23 wherein the second dielectric material can be removed selective to the first dielectric material.

27. The method of claim 22 comprises:

an intermediate layer below the device layer, the intermediate layer comprises a dielectric material.

28. The method of claim 22 wherein depositing the fill material comprises a high density plasma (HDP) deposition process.

29. The method of claim 22 comprises further processing to form a liquid crystal device.

30. The method of claim 22 wherein removing the excess fill material comprises chemical mechanical polishing.

31. A method of fabricating a semiconductor device comprising:

providing a substrate prepared with a device layer, first and second sublayers on the device layer and an opening in the device layer, wherein the first and second sublayers are formed on the device layer prior to forming the opening in the device layer;

depositing a fill material to form a fill layer, the fill material filling the opening;

removing excess fill material of the fill layer, wherein removing the excess fill material includes removing portions of the second sublayer to expose the first sublayer over the device layer and to form a substantially planar top surface of the semiconductor device.

32. The method of claim 31 wherein:

the device layer comprises a reflective layer;

the first sublayer comprises a first dielectric material; and

the second sublayer comprises a second dielectric material.

33. The method of claim 32 wherein the reflective layer comprises a conductive material.

34. The method of claim 32 wherein the reflective layer comprises a conductive material selected from Al, AlCuSi or AlCu.

35. The method of claim 32 wherein the second dielectric material can be removed selective to the first dielectric material.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 19, 2020
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
Reel/Frame 054481/0673 →
SECURITY AGREEMENT Recorded Nov 27, 2018
From: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
To: WILMINGTON TRUST, NATIONAL ASSOCIATION
Reel/Frame 047660/0203 →
CHANGE OF NAME Recorded Jun 2, 2011
From: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.
To: CHARTERED SEMICONDUCTOR MANUFACTURING PTE. LTD.
Reel/Frame 026374/0124 →
CHANGE OF NAME Recorded Jun 2, 2011
From: CHARTERED SEMICONDUCTOR MANUFACTURING PTE. LTD.
To: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
Reel/Frame 026374/0135 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 10, 2008
From: LIM, SIN LENG; KIM, IN KI; PARK, JONG SUNG; KIM, MIN HWAN; LU, WEI
To: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
Reel/Frame 021075/0504 →