Latch-up immunity nLDMOS

1. A method comprising:

providing in a substrate a dual voltage n-well (DVNW) region;

providing a high voltage p-well (HVPW) region in the DVNW region;

providing bulk and source regions in the HVPW region;

providing a drain region in the DVNW region, separate from the HVPW region;

providing a polysilicon gate over a portion of the HVPW region and the DVNW region; and

providing in the source region in the HVPW region, second and third N+ regions and a first P+ region, the second and third N+ regions being separated by the first P+ region.

2. The method according to claim 1 , comprising:

providing in the DVNW region in the drain region an n-well (NW) region.

3. The method according to claim 2 , comprising:

providing a first N+ region in the NW region.

4. The method according to claim 3 , comprising:

forming a silicided block layer on the first N+ region, a portion of the polysilicon gate, and the DVNW therebetween.

5. The method according to claim 1 , comprising:

coupling the second and third N+ regions and the polysilicon gate to a ground rail; and

coupling the first N+ region to an I/O pad.

6. The method according to claim 5 , further comprising:

providing a second P+ region in the substrate, separate from the DVNW region; and

coupling the second P+ region to the ground rail.

7. The method according to claim 6 , comprising:

providing an ESD current path from the I/O pad to the ground rail through the NW, DVNW, HVPW, and third N+ regions during an ESD event.

8. The method according to claim 1 , wherein the first P+ region and the second N+ region abut each other, having no other element therebetween.