Hybrid transistor
View Patent ↗A method of forming a device is disclosed. The method includes providing a substrate having an active area. A gate is formed on the substrate. First and second current paths through the gate are formed. The first current path serves a first purpose and the second current path serves a second purpose. The gate controls selection of the current paths.
1. A device comprising:
a memory cell having a hybrid transistor, wherein the transistor includes
a substrate having an active area,
a gate on the substrate, and
first and second current paths through the gate, wherein the first current path serves a first purpose and the second current path serves a second purpose, the current paths are selected by providing an appropriate signal at the gate.
2. The device of claim 1 wherein the transistor comprises:
first and second source regions adjacent to a first side of the gate; and
a drain region adjacent to a second side of the gate.
3. The device of claim 2 wherein the transistor comprises an ionization region disposed between the second source region and the gate.
4. The device of claim 2 wherein the transistor comprises at least four terminals, wherein the first and second terminals are coupled to first and second source regions, the third terminal is coupled to a drain region, and the fourth terminal is coupled to the gate.
5. The device of claim 4 wherein:
the first current path is used for programming the memory cell; and
the second current path is used for reading the memory cell.
6. The device of claim 5 wherein:
the first current path is formed through the first, fourth and the third terminal; and
the second current path is formed through the second, fourth and the third terminal.
7. The device of claim 1 wherein the transistor includes:
a first sub-transistor comprising a transistor having first source and drain regions comprising dopants of the same polarity type; and
a second sub-transistor comprising an impact ionization transistor having second source and drain regions comprising dopants of the opposite polarity types.
8. The device of claim 7 wherein the impact ionization transistor comprises a P-I-N diode including an intrinsic region between doped regions of first and second polarity types.
9. The device of claim 7 wherein the gate comprises first and second sub-gate electrodes.
10. The device of claim 9 wherein:
the first sub-gate electrode serves as a control gate; and
the second sub-gate electrode serves as a floating gate.
11. The device of claim 7 wherein the second source region comprises an elevated doped region in an upper portion of a raised region.
12. A method of forming a device comprising:
forming a memory cell having a hybrid transistor, wherein forming the memory cell includes
providing a substrate having an active area,
forming a gate on the substrate, and
forming first and second current paths through the gate, the first current path serves a first purpose and the second current path serves a second purpose, wherein the gate controls selection of the current paths.
13. The method of claim 12 wherein the transistor comprises:
first and second source regions adjacent to a first side of the gate; and
a drain region adjacent to a second side of the gate.
14. The method of claim 13 wherein the transistor comprises an ionization region disposed between the second source region and the gate.
15. The method of claim 13 wherein the substrate comprises a crystalline-on-insulator substrate.
16. The method of claim 15 wherein the transistor comprises a FinFET.
17. The method of claim 16 wherein the transistor comprises an elevated body disposed on a buried oxide layer of the substrate, the body portion is wrapped around by the gate and separated into first and second sections.
18. The method of claim 17 comprises forming sidewall spacers on sidewalls of the gate.
19. The method of claim 18 comprises:
performing a angled implant of first polarity type dopants into the substrate, forming the second source region and an intrinsic region beneath the spacers;
performing a first angled implant of second polarity type dopants into the substrate, forming the first source region and partially the drain region; and
performing a further plurality of angled implants of second polarity type dopants into the substrate, completing the formation of the drain region.
20. The method of claim 12 wherein the transistor comprises at least four terminals, wherein the first and second terminals are coupled to first and second source regions, the third terminal is coupled to a drain region, and the fourth terminal is coupled to the gate.
21. The method of claim 20 wherein:
the first current path is formed through the first, fourth and the third terminal; and
the second current path is formed through the second, fourth and the third terminal.
22. The method of claim 12 wherein:
the first current path is used for programming the memory cell; and
the second current path is used for reading the memory cell.
23. The method of claim 12 wherein the transistor includes:
a first sub-transistor comprising a transistor having first source and drain regions comprising dopants of the same polarity type; and
a second sub-transistor comprising an impact ionization transistor having second source and drain regions comprising dopants of the opposite polarity types.
24. The method of claim 23 wherein the impact ionization transistor comprises a P-I-N diode including an intrinsic region between doped regions of first and second polarity types.
25. The method of claim 23 wherein the gate comprises first and second sub-gate electrodes.
26. The method of claim 25 wherein:
the first sub-gate electrode serves as a control gate; and
the second sub-gate electrode serves as a floating gate.
27. The method of claim 23 wherein the second source region comprises an elevated doped region in an upper portion of a raised region.
28. The method of claim 27 comprises:
performing a first implant to implant second type dopants into the substrate, forming the first source and drain regions; and
performing a second implant to implant first type dopants into the substrate, forming the second source region.
29. The method of claim 28 wherein the intrinsic region comprises an lower portion of the raised region and substrate.
30. A method of forming an integrated circuit comprising:
forming a memory cell having a hybrid transistor, wherein forming the memory cell includes
providing a substrate having an active area,
forming a gate on the substrate, and
forming first and second current paths through the gate, the first current path serves a first purpose and the second current path serves a second purpose, wherein the gate controls selection of the current paths.