Method to tune narrow width effect with raised S/D structure
View Patent ↗A method (and semiconductor device) of fabricating a semiconductor device adjusts gate threshold (Vt) of a field effect transistor (FET) with raised source/drain (S/D) regions. A halo region is formed in a two-step process that includes implanting dopants using conventional implantation techniques and implanting dopants at a specific twist angle. The dopant concentration in the halo region near the active edge of the raised S/D regions is higher and extends deeper than the dopant concentration within the interior region of the raised S/D regions. As a result, Vt near the active edge region is adjusted and different from the Vt at the active center regions, thereby achieving same or similar Vt for a FET with different width.
1. A field-effect transistor (FET) device comprising:
a substrate of a first conductivity type and defining a channel surface;
a gate structure having a dielectric layer and a gate electrode disposed on the substrate;
a first raised source/drain (S/D) region and a second raised S/D region having a channel formed beneath the gate structure, the first and second raised S/D regions of a second conductivity type;
a halo region having dopants of the first conductivity type and extending along at least a portion of the gate structure from one edge of the first raised S/D region to another edge of the first raised S/D region, the halo region comprising:
first dopants of the first conductivity type implanted within the substrate at a first predetermined tilt angle and at a first predetermined twist angle substantially equal to zero degrees relative to a direction perpendicular to the gate width, and
second dopants of the first conductivity type implanted at a second predetermined tilt angle and at a second predetermined twist angle of between about 20 and 70 degrees; and
wherein a doping concentration in the halo region near a center region of the first raised S/D region at a given depth below the channel surface is lower than a doping concentration in the halo region near an edge of the first raised S/D region at the given depth, such that the FET has a gate threshold (Vt) near the center region that is different than a Vt near the edge of the first raised S/D region.
2. The device in accordance with claim 1 wherein the FET has a gate threshold (Vt) near the center region that is lower than a Vt near the edge of the first raised S/D region.
3. The device in accordance with claim 1 wherein the first and second raised S/D regions each include an extension region of a second conductivity type and extending underneath the gate structure.
4. The device in accordance with claim 1 wherein the gate structure extends laterally beyond an edge of the first raised S/D region and an edge of the second raised S/D region.
5. The device in accordance with claim 1 wherein the first and second raised S/D regions are at least partially surrounded by a shallow trench isolation structure.
6. A semiconductor device, comprising:
a substrate of a first conductivity type;
a field effect transistor (FET) structure formed thereon and comprising a gate having a gate width, a first raised source/drain (S/D) region and a second raised S/D region, the first and second raised S/D regions of a second conductivity type;
a halo region having dopants of the first conductivity type disposed within the substrate, wherein the halo region comprises:
first dopants of the first conductivity type implanted at a first predetermined tilt angle and at a first predetermined twist angle substantially equal to zero degrees relative to a direction perpendicular to the gate width to form a first portion of the halo region, and
second dopants of the first conductivity type implanted at a second predetermined tilt angle and at a second predetermined twist angle to form a second portion of the halo region, such that a doping concentration at a given depth below a channel surface near a center of the first raised S/D region is lower than a doping concentration at the given depth below the channel surface near an edge of the first raised S/D region.
7. The device in accordance with claim 6 wherein the second predetermined twist angle is between about 20 and 70 degrees.
8. The device in accordance with claim 7 wherein the second predetermined twist angle is about 45 degrees.
9. The device in accordance with claim 6 wherein the first predetermined tilt angle is equal to the second predetermined tilt angle.
10. The device in accordance with claim 9 wherein the second predetermined twist angle is between about 20 and 70 degrees.
11. The device in accordance with claim 6 wherein the device has a gate threshold (Vt) near the center of the first raised S/D region that is lower than a Vt near the edge of the first raised S/D region.
12. The device in accordance with claim 6 wherein the first and second raised S/D regions each include an extension region of a second conductivity type and extending underneath the gate.
13. The device in accordance with claim 6 wherein the gate extends laterally beyond an edge of the first raised S/D region and an edge of the second raised S/D region.
14. The device in accordance with claim 6 wherein the first and second raised S/D regions are at least partially surrounded by a shallow trench isolation structure.
15. A field-effect transistor (FET) comprising:
a substrate of a first conductivity type;
a FET structure comprising a gate having a gate width, a first raised source/drain (S/D) region and a second raised S/D region, the first and second raised S/D regions of a second conductivity type; and
a halo region disposed in the substrate and having dopants of the first conductivity type, the halo region comprising:
first dopants of the first conductivity type implanted within the substrate at a first predetermined tilt angle and at a first predetermined twist angle substantially equal to zero degrees relative to a direction perpendicular to the gate width, and
second dopants of the first conductivity type implanted at a second predetermined tilt angle and at a second predetermined twist angle of between about 20 and 70 degrees.
16. The FET in accordance with claim 15 wherein a doping concentration at a predetermined depth below a channel surface near a center of the first raised S/D region is lower than a doping concentration at the predetermined depth near an edge of the first raised S/D region.
17. The FET in accordance with claim 15 wherein the second predetermined twist angle is about 45 degrees, and the first predetermined tilt angle is equal to the second predetermined tilt angle.
18. The FET in accordance with claim 15 wherein the raised S/D regions are at least partially surrounded by a shallow trench isolation structure.
19. The FET in accordance with claim 15 wherein the device has a gate threshold (Vt) near a center of the first raised S/D region that is lower than a Vt near the edge of the first raised S/D region.
20. The FET in accordance with claim 19 wherein:
the first and second raised S/D regions each include an extension region of a second conductivity type and extending underneath the gate; and
the gate extends laterally beyond an edge of the first raised S/D region and an edge of the second raised S/D region.