MRAM with metal-insulator-transition material
View Patent ↗Memory cells and methods for forming a memory cell are disclosed. The memory cell includes a first selector having a first gate coupled to a first word line (WL) and first and second source/drain (S/D) regions, and a second selector having a second gate coupled to a second WL and first and second S/D regions. The second S/D regions of the first and the second selectors are a common S/D region. The first and the second WLs are a common WL and the second S/D regions of the first and second selectors are coupled to a source line (SL). The memory cell includes a storage element which includes a magnetic tunnel junction (MTJ) element coupled with a bit line (BL) and the first and the second selectors, and a voltage control switch which includes a metal-insulator-transition (MIT) material coupled with the first selector.
1. A memory cell comprising:
a first selector having a first gate coupled to a word line (WL) and first selector first and second source/drain (S/D) regions;
a second selector having a second gate coupled to the WL and second selector first and second S/D regions, wherein the first selector and the second selector second S/D regions are coupled to a source line (SL);
a storage element which comprises a magnetic tunnel junction (MTJ) element having first and second MTJ terminals, the first MTJ terminal is coupled to the first selector and the second selector first S/D regions and the second MTJ terminal is coupled to a bit line (BL); and
a voltage control switch, wherein the voltage control switch,
during a write operation, causes the first selector to be on, and
during a read operation, causes the first selector to be off and the second selector to be on.
2. The memory cell of claim 1 wherein the voltage control switch comprises a phase transition switch such that it is in conductive state when subject to high voltage and in insulating state when subject to low voltage.
3. The memory cell of claim 1 wherein:
the voltage control switch comprises first and second switch terminals, the first switch terminal is coupled to the first selector second S/D region and the second switch terminal is coupled to the SL; and
during the write operation, the second selector is off.
4. The memory cell of claim 3 wherein the voltage control switch comprises a phase transition switch having a metal-insulator-transition (MIT) material.
5. The memory cell of claim 4 wherein the MIT material is disposed in a metal level, wherein the metal level is the same metal level where the SL is disposed and the MIT material is disposed below the SL.
6. The memory cell of claim 1 wherein:
the voltage control switch comprises first and second switch terminals, the first switch terminal is coupled to the first gate and the second switch terminal is coupled to the WL; and
during the write operation, the second selector is on.
7. The memory cell of claim 6 wherein the voltage control switch comprises a phase transition switch having a metal-insulator-transition (MIT) material.
8. The memory cell of claim 7 wherein the first gate of the first selector comprises a first gate electrode and a first gate dielectric, wherein the MIT material is disposed in between the first gate electrode and the first gate dielectric.
9. The memory cell of claim 1 wherein the first and the second selectors are coupled electrically in parallel between the SL and the BL.
10. The memory cell of claim 1 wherein the first selector and the second selector first S/D regions are a common S/D region.
11. The memory cell of claim 1 comprising first and second selector transistors aligned adjacent in an x-direction within a cell region.
12. A memory cell comprising:
a first selector having a first gate coupled to a word line (WL) and first selector first and second source/drain (S/D) regions;
a second selector having a second gate coupled to the WL and second selector first and second S/D regions, wherein the first selector and the second selector second S/D regions are coupled to a source line (SL);
a storage element having first and second storage terminals, the first storage terminal is coupled to the first selector and the second selector first S/D regions and the second storage terminal is coupled to a bit line (BL); and
a voltage control switch, wherein the voltage control switch,
during a write operation, causes the first selector to be on, and
during a read operation, causes the first selector to be off and the second selector to be on.
13. The memory cell of claim 12 wherein the storage element comprises a magnetic tunnel junction (MTJ) element.
14. The memory cell of claim 12 wherein the voltage control switch comprises a phase transition switch with a metal insulator transition (MIT) material having a phase transition characteristic such that it is in conductive state when subject to high voltage and in insulating state when subject to low voltage.
15. The memory cell of claim 12 wherein:
the voltage control switch comprises first and second switch terminals, the first switch terminal is coupled to the first selector second S/D region and the second switch terminal is coupled to the SL; and
during the write operation, the second selector is off.
16. The memory cell of claim 15 wherein the voltage control switch comprises a phase transition switch having a metal-insulator-transition (MIT) material, wherein the MIT material is disposed in a metal level, wherein the metal level is the same metal level where the SL is disposed and the MIT material is disposed below the SL.
17. The memory cell of claim 16 wherein:
the voltage control switch comprises first and second switch terminals, the first switch terminal is coupled to the first gate and the second switch terminal is coupled to the WL; and
during the write operation, the second selector is on.
18. The memory cell of claim 17 wherein the voltage control switch comprises a phase transition switch having a metal-insulator-transition (MIT) material, the voltage control switch is disposed between a first gate electrode and a first gate dielectric of the first gate.
19. The memory cell of claim 12 wherein the first selector and the second selector first S/D regions are a common S/D region.
20. A memory cell comprising:
a first selector having a first gate coupled to a word line (WL) and first and second source/drain (S/D) regions;
a second selector having a second gate coupled to the WL and first and second S/D regions, wherein the second S/D regions of the first and the second selectors are a common S/D region, the common S/D region of the first and second selectors is coupled to a source line (SL);
a storage element which comprises a magnetic tunnel junction (MTJ) element is coupled with a bit line (BL) and the first and the second selectors; and
a voltage control switch which comprises a metal-insulator-transition (MIT) material coupled to the first selector, wherein the voltage control switch is a phase transition switch, wherein the MIT material comprises a phase transition characteristic such that it is in conductive state when subject to high voltage and in insulating state when subject to low voltage.