Integration of high voltage trench transistor with low voltage CMOS transistor

1. A method of forming a device comprising:

providing a substrate defined with a device region, wherein the device region comprises a first polarity type first doped well;

forming a gate having an upper and a lower portion in a trench in the substrate, wherein the upper portion forms a gate electrode and the lower portion forms a gate field plate;

forming second and third doped wells disposed within the first doped well, wherein

the second doped well comprises first polarity type dopants and the third doped well comprises second polarity type dopants,

the second doped well comprises a dopant concentration different to the first doped well, and

the third doped well comprises a depth shallower than the gate electrode;

forming first and second surface doped regions adjacent to the gate; and

wherein the gate field plate introduces a vertical reduced surface (RESURF) effect in a drift region of the device.

2. The method of claim 1 further comprising forming a buried doped region in the substrate.

3. The method of claim 2 wherein the buried doped region is disposed below the gate.

4. The method of claim 1 wherein the device region is surrounded by device isolation regions.

5. The method of claim 4 wherein the device region comprises one or more internal device isolation regions, dividing the device region into multiple device sub-regions.

6. The method of claim 5 comprising:

forming an intermediate voltage device and a low voltage device in the multiple device sub-regions, wherein the intermediate voltage device and the low voltage device comprise

a gate having a gate electrode and gate dielectric,

source/drain regions adjacent to the gate, and

a channel disposed in the substrate under the gate between the source/drain regions.

7. The method of claim 4

wherein the second surface doped region is disposed in the second doped well and the first surface doped region is disposed in the third doped well.

8. The method of claim 1 wherein forming the gate in the trench comprises:

forming the trench in the first doped well, the trench having an upper and a lower portion;

forming a first gate dielectric in the upper portion of the trench adjacent to the first surface doped region;

forming a second gate dielectric layer in the upper portion of the trench adjacent to the second surface doped region and the lower portion of the trench;

forming the gate electrode having upper and lower portions in the trench;

wherein the first gate dielectric lines an inner edge of the upper gate electrode; and

wherein the second gate dielectric surrounds the lower gate electrode and an outer edge of the upper gate electrode.

9. The method of claim 8 wherein the first gate dielectric wraps around to line a portion of the bottom of the upper gate electrode.

10. The method of claim 8 wherein the second gate dielectric is a multi-layered dielectric stack.

11. The method of claim 10 wherein the second gate dielectric is an oxide-nitride-oxide (ONO) stack.

12. The method of claim 8 wherein forming the trench comprises:

forming the upper portion of the trench, wherein exposed sidewalls of the trench are lined with a gate dielectric layer;

lining a spacer layer on the gate dielectric layer;

forming a sidewall spacer on a first sidewall of the upper portion of the trench adjacent to the first surface doped region; and

etching the substrate to form the lower portion of the trench, wherein the sidewall spacer serves as an etching mask.

13. The method of claim 1 wherein an inner edge of the gate field plate is offset from an inner edge of the gate electrode.

14. A method of forming a semiconductor device comprising:

providing a substrate defined with a device region, wherein the device region comprises a first polarity type first doped well;

forming a gate having an upper and a lower portion in a trench in the substrate, the upper portion forms a gate electrode and the lower portion forms a gate field plate, wherein an inner edge of the gate field plate is offset from an inner edge of the gate electrode;

forming second and third doped wells disposed within the first doped well, wherein

the second doped well comprises first polarity type dopants and the third doped well comprises second polarity type dopants,

the second doped well comprises a dopant concentration different to the first doped well, and

the third doped well comprises a depth shallower than the gate electrode;

forming first and second surface doped regions adjacent to the gate; and

wherein the gate field plate introduces a vertical reduced surface (RESURF) effect in a drift region of the device.

15. The method of claim 14 wherein forming the gate in the trench comprises:

forming the trench in the substrate, the trench having an upper and a lower portion;

forming a first gate dielectric in the upper portion of the trench adjacent to the first surface doped region;

forming a second gate dielectric layer in the upper portion of the trench adjacent to the second surface doped region and the lower portion of the trench;

forming the gate electrode having upper and lower portions in the trench;

wherein the first gate dielectric lines an inner edge of the upper gate electrode; and

wherein the second gate dielectric surrounds the lower gate electrode and an outer edge of the upper gate electrode.

16. The method of claim 15 wherein the first gate dielectric wraps around to line a portion of the bottom of the upper gate electrode.

17. The method of claim 15 wherein the second gate dielectric is a multi-layered dielectric stack.

18. The method of claim 17 wherein the second gate dielectric is an oxide-nitride-oxide (ONO) stack.

19. A semiconductor device comprising:

a substrate comprising a first polarity type first doped well;

a gate having an upper and a lower portion in a trench in the substrate, wherein the upper portion forms a gate electrode and the lower portion forms a gate field plate;

second and third doped wells disposed within the first doped well, wherein

the second doped well comprises first polarity type dopants and the third doped well comprises second polarity type dopants,

the second doped well comprises a dopant concentration different to the first doped well, and

the third doped well comprises a depth shallower than the gate electrode;

first and second surface doped regions adjacent to the gate; and

wherein the gate field plate introduces a vertical reduced surface (RESURF) effect in a drift region of the device.

20. The semiconductor device of claim 19 wherein the second surface doped region is disposed in the second doped well and the first surface doped region is disposed in the third doped well.