Simple and cost-free MTP structure

1. A non-volatile (NV) multi-time programmable (MTP) memory cell comprising:

a substrate;

first and second wells disposed in the substrate;

a first transistor having a select gate and a second transistor having a floating gate adjacent one another and disposed over the second well, wherein the first and second transistors are coupled in series and share a common diffusion region; and

a control gate disposed over the first well, wherein the control gate is coupled to the floating gate and the control and floating gates comprise the same gate layer extending across the first and the second wells; and

at least one well contact region disposed in the first well and adjacent to the control gate, wherein the well contact region couples the first well to a control gate line (CGL) and is biased at a bias potential during various operations of the memory cell.

2. The memory cell of claim 1 wherein the first well is of a first polarity type and the second well is of a second polarity type different from the first polarity type.

3. The memory cell of claim 2 , wherein the first well is an n-type well and the second well is a p-type well, wherein each of the floating gate and the select gate comprises an n-type metal-oxide-semiconductor (NMOS), and wherein the control gate comprises an n-type capacitor.

4. The memory cell of claim 3 , wherein the memory cell is programmable by Fowler-Nordheim (FN) tunneling effect.

5. The memory cell of claim 3 , wherein the memory cell is erasable by FN tunneling effect.

6. A non-volatile (NV) multi-time programmable (MTP) memory cell comprising:

a substrate;

first and second wells disposed in the substrate, wherein the first well is an n-type well and the second well is a p-type well;

a first transistor having a select gate and a second transistor having a floating gate adjacent one another and disposed over the second well and sharing a common diffusion region; and

a control gate disposed over the first well, wherein the control gate is coupled to the floating gate and the control and floating gates comprise the same gate layer extending across the first and the second wells, and wherein

each of the floating gate and the select gate comprises an n-type metal-oxide-semiconductor (NMOS), and the control gate comprises an n-type capacitor,

an area ratio between the control gate and the floating gate is 0.8:0.2, a ratio of width and length of the floating gate is 0.4:0.28, and a ratio of width and length of the control gate is 1.6:0.84.

7. The memory cell of claim 3 comprising a plurality of contacts surrounding the control gate, wherein the plurality of contacts are coupled to the first well of the control gate.

8. The memory cell of claim 1 wherein the first and second wells comprise the same polarity type.

9. The memory cell of claim 8 , wherein the first well is an n-type well and the second well is an n-type well, wherein each of the floating gate and the select gate comprises a p-type metal-oxide-semiconductor (PMOS), and wherein the control gate comprises a p-type capacitor.

10. The memory cell of claim 9 , wherein the floating gate is doped with p-type dopants.

11. The memory cell of claim 9 , wherein the memory cell is programmable by band-to-band tunneling induced hot electron (BTBTHE) injection.

12. The memory cell of claim 9 , wherein the memory cell is erasable by FN tunneling effect.

13. The memory cell of claim 8 , wherein the first well is an n-type well and the second well is an n-type well, wherein each of the floating gate and the select gate comprises a p-type metal-oxide-semiconductor (PMOS), and wherein the control gate comprises an n-type capacitor.

14. The memory cell of claim 13 , wherein the floating gate is doped with n-type dopants.

15. The memory cell of claim 1 comprising:

a third well disposed in the substrate; and

an erase gate disposed over the third well, wherein the control, floating and erase gates are commonly coupled and the control, floating and erase gates comprise the same gate layer extending across the first, second and third wells.

16. The memory cell of claim 15 , wherein each of the first and the third wells is a p-type well and wherein the second well is an n-type well.

17. The memory cell of claim 16 , wherein each of the floating gate and the select gate comprises a p-type metal-oxide-semiconductor (PMOS).

18. The memory cell of claim 17 , wherein each of the control gate and the erase gate comprises a p-type capacitor.

19. A non-volatile (NV) multi-time programmable (MTP) memory cell comprising:

a substrate;

first and second wells disposed in the substrate;

a first transistor having a select gate and a second transistor having a floating gate adjacent one another and disposed over the second well; and

a control gate disposed over the first well, wherein the control gate is coupled to the floating gate and the control and floating gates comprise the same gate layer extending across the first and second wells, and

wherein a ratio of width and length of the floating gate is 0.4:0.28, and wherein a ratio of width and length of the control gate is 1.6:0.84.

20. The memory cell of claim 19 comprising:

a third well disposed in the substrate; and

an erase gate disposed over the third well, wherein the control, floating and erase gates are commonly coupled.

21. The memory cell of claim 1 wherein the memory cell is configured to operate in two types of programming modes or two types of erase modes.

22. The memory cell of claim 1 wherein:

the first transistor comprises first and second diffusion regions and the second transistor comprises first and second diffusion regions;

the second diffusion regions of the first and second transistors correspond to the common diffusion region;

the first diffusion region of the first transistor is coupled to a bitline while the first diffusion region of the second transistor is coupled to a source line of the memory cell; and

the well contact region coupled to the CGL is biased at a positive programming potential (+V prog ) during programming of the memory cell.