Integrated circuit system employing low-k dielectrics and method of manufacture thereof

1. A method of manufacture of an integrated circuit system comprising:

fabricating a substrate having an integrated circuit;

applying a low-K dielectric layer over the integrated circuit;

forming a via and a trench, in the low-K dielectric layer, over the integrated circuit;

forming a structure surface by a chemical-mechanical planarization (CMP) process; and

applying a direct implant through the structure surface for forming an implant layer and a metal passivation layer including repairing damage, to the low-K dielectric layer, caused by the CMP process.

2. The method as claimed in claim 1 further comprising forming a dielectric capping layer on the structure surface.

3. The method as claimed in claim 1 further comprising depositing an interconnect metal in the low-K dielectric layer for forming the via and the trench.

4. The method as claimed in claim 1 wherein forming the via and the trench includes depositing a diffusion barrier layer on an opening in the low-K dielectric layer.

5. The method as claimed in claim 1 wherein applying the direct implant through the surface structure includes implanting an inert element, an electron scavenger, a negative element, or a combination thereof classified to be a non-metal or a metalloid for physically and chemically altering the implant layer and the metal passivation layer.

6. A method of manufacture of an integrated circuit system comprising:

fabricating a substrate having an integrated circuit;

applying a low-K dielectric layer over the integrated circuit including applying a low-K dielectric material or an ultra low-K dielectric material for forming the low-K dielectric layer;

forming a via and a trench, in the low-K dielectric layer, over the integrated circuit;

forming a structure surface by a chemical-mechanical planarization (CMP) process including forming a planar surface including the via, the trench, and the low-K dielectric layer;

forming a dielectric capping layer above the structure surface; and

applying a direct implant through the dielectric capping layer and through the structure surface for forming an implant layer and a metal passivation layer including repairing damage, to the low-K dielectric layer, caused by the CMP process.

7. The method as claimed in claim 6 further comprising depositing an interconnect metal in the low-K dielectric layer for forming the via and the trench including depositing copper for the interconnect metal.

8. The method as claimed in claim 6 wherein forming the via and the trench includes depositing a diffusion barrier layer on an opening in the low-K dielectric layer including forming a vertical sidewall in the low-K dielectric layer for the via and the trench.

9. The method as claimed in claim 6 wherein applying the direct implant through the surface structure by implanting a dopant for physically and chemically altering the implant layer and the metal passivation layer including preventing time-dependent-dielectric-breakdown (TDDB) and electro-migration (EM).

10. An integrated circuit system comprising:

a substrate having an integrated circuit;

a low-K dielectric layer over the integrated circuit;

a via and a trench over the integrated circuit;

a structure surface formed, by a chemical-mechanical planarization (CMP) process, on the via, the trench, and the low-K dielectric layer; and

an implant layer and a metal passivation layer below the structure surface formed by a direct implant through the structure surface.

11. The system as claimed in claim 10 further comprising a dielectric capping layer on the structure surface.

12. The system as claimed in claim 10 further comprising an interconnect metal deposited in the low-K dielectric layer for the via and the trench.

13. The system as claimed in claim 10 wherein the via and the trench formed in the low-K dielectric layer includes a diffusion barrier layer on an opening in the low-K dielectric layer.

14. The system as claimed in claim 10 wherein the implant layer and the metal passivation layer formed by the direct implant through the structure surface includes an inert element, an electron scavenger, a negative element, or a combination thereof classified to be a non-metal or a metalloid implanted for physically and chemically altering the implant layer and the metal passivation layer.

15. The system as claimed in claim 10 further comprising:

a low-K dielectric material or an ultra low-K dielectric material in the low-K dielectric layer; and

a planar surface formed by the CMP process includes the via, the trench and the low-K dielectric layer are coplanar.

16. The system as claimed in claim 15 further comprising a dielectric capping layer on the structure surface.

17. The system as claimed in claim 15 further comprising an interconnect metal deposited in the low-K dielectric layer for the via and the trench includes the interconnect metal is copper.

18. The system as claimed in claim 15 wherein the via and the trench formed in the low-K dielectric layer includes a diffusion barrier layer on an opening in the low-K dielectric layer with a vertical sidewall formed in the low-K dielectric layer.

19. The system as claimed in claim 10 wherein the implant layer and the metal passivation layer formed by the direct implant through the structure surface includes an inert element, an electron scavenger, a negative element, or a combination thereof classified to be a non-metal or a metalloid implanted for physically and chemically altering the implant layer and the metal passivation layer.