MOS with recessed lightly-doped drain
View Patent ↗LDD regions are provided with high implant energy in devices with reduced thickness poly-silicon layers and source/drain junctions. Embodiments include forming an oxide layer on a substrate surface, forming a poly-silicon layer over the oxide layer, forming first and second trenches through the oxide and poly-silicon layers and below the substrate surface, defining a gate region therebetween, implanting a dopant in a LDD region through the first and second trenches, forming spacers on opposite side surfaces of the gate region and extending into the first and second trenches, and implanting a dopant in a source/drain region below each of the first and second trenches.
1. A method comprising:
forming an oxide layer on a substrate surface;
forming a poly-silicon layer over the oxide layer;
forming first and second trenches through the oxide and poly-silicon layers and below the substrate surface, defining a gate region therebetween;
implanting a dopant in a lightly doped drain (LDD) region through the first and second trenches;
forming spacers on opposite side surfaces of the gate region and extending into the first and second trenches; and
implanting a dopant in a source/drain region below each of the first and second trenches.
2. The method according to claim 1 , further comprising:
forming a silicide in the first and second trenches, subsequent to implanting the dopant in the source/drain regions.
3. The method according to claim 1 , comprising:
forming the first and second trenches by:
forming a mask over the oxide and poly-silicon layers, the mask leaving exposed regions defining the first and second trenches, and
etching the poly-silicon layer, the oxide layer, and the substrate;
implanting the dopant in the LDD region; and
removing the mask.
4. The method according to claim 1 , comprising:
forming the first and second trenches to a depth of 10 nm to 200 nm below the substrate surface and to a width of 0.2 μm to 0.6 μm.
5. The method according to claim 1 , comprising implanting the dopant in the LDD region at energies of 30 kiloelectron volts (keV) to 300 keV.
6. The method according to claim 1 , further comprising:
forming first and second well regions in the substrate, prior to forming the oxide layer;
forming the oxide layer to a greater thickness over the first well region than over the second well region; and
forming the first and second trenches in the first well region.
7. The method according to claim 6 , further comprising:
patterning a second gate region in the poly-silicon and oxide layers over the second well region;
forming a mask over the substrate, the mask leaving exposed the second gate region and the substrate surface around the second gate region; and
implanting a dopant in the substrate around the second gate region, forming a second LDD region.
8. A method comprising:
forming an oxide layer on a substrate surface;
forming a poly-silicon layer over the oxide layer;
implanting a dopant in a lightly doped drain (LDD) region in the substrate through the oxide and poly-silicon layers;
forming first and second trenches in the oxide and poly-silicon layers and in a portion of substrate below the substrate surface, defining a gate region therebetween;
forming spacers on opposite side surfaces of the gate region and extending into the first and second trenches; and
implanting a dopant in a source/drain region below each of the first and second trenches.
9. The method according to claim 8 , further comprising:
forming a silicide in the first and second trenches, subsequent to implanting the dopant in the source/drain regions.
10. The method according to claim 8 , comprising:
forming a mask over the oxide and poly-silicon layers, prior to implanting the LDD region, the mask leaving exposed regions defining the first and second trenches.
11. The method according to claim 10 , comprising:
forming the poly-silicon layer to a thickness of 0.05 μm to 0.3 μm.
12. The method according to claim 11 , comprising:
implanting the dopant in the LDD regions at energies of 100 kiloelectron volts (keV) to 400 keV.
13. The method according to claim 8 , comprising:
forming the first and second trenches to a depth of 10 nm to 200 nm below the substrate surface and a width of 0.2 μm to 0.6 μm.
14. The method according to claim 8 , further comprising:
forming first and second well regions in the substrate, prior to forming the oxide layer;
forming the oxide layer to a greater thickness over the first well region than over the second well region; and
forming the first and second trenches in the first well region.
15. The method according to claim 14 , comprising:
patterning a second gate region in the poly-silicon and oxide layers over the second well region;
forming a mask over the substrate, the mask leaving exposed the second gate region and the substrate surface around the second gate region; and
implanting a dopant in the substrate around the second gate region, forming a second LDD region.