Edge structure for backgrinding asymmetrical bonded wafer
View Patent ↗Semiconductor devices and methods of forming a semiconductor device are disclosed. The device includes a wafer with top and bottom surfaces. The wafer includes edge and non-edge regions. The wafer includes a plurality of devices and partially processed TSV contacts disposed in the non-edge region and a groove disposed at the edge region. The groove enables edges of the wafer to be automatically trimmed off as the wafer is subject to a back-grinding planarization process to expose the TSV contacts in the non-edge region of the wafer.
1. A method of forming a semiconductor device comprising:
providing first and second wafers with top and bottom surfaces, the wafers include edge and non-edge regions, the edge region is at a periphery of the wafers, the edge region surrounds the non-edge region of the wafers, wherein the first and second wafers include devices formed on a top surface of the wafer in the non-edge region;
forming a groove at the edge region and partially processed through silicon via (TSV) contacts at the non-edge region of the first wafer, top surfaces of the TSV contacts are exposed, wherein the second wafer is devoid of the groove;
bonding the first and second wafers to form a device stack; and
subjecting the bottom surface of the first wafer to a back-grinding process, wherein the groove in the edge region of the first wafer enables edges of the first wafer to be automatically trimmed off as the back-grinding process exposes the TSV contacts in the non-edge region of the first wafer.
2. The method of claim 1 further comprising forming partially processed TSV contacts at the non-edge region of the second wafer and subjecting the bottom surface of the second wafer to a back-grinding process.
3. The method of claim 1 wherein forming the partially processed TSV contacts comprises forming a plurality of TSV holes which extend from the top surface and partially through the wafer and filling the TSV contact holes with a conductive layer.
4. The method of claim 3 wherein the groove is formed simultaneously with the plurality of TSV holes and the devices in the non-edge region.
5. The method of claim 3 wherein the groove is formed before or after the formation of the plurality of TSV holes and the devices in the non-edge region.
6. The method of claim 1 wherein the groove comprises a depth D G of about 0.010 mm-0.5 mm and a width W G of about 0.010 mm-0.5 mm.
7. The method of claim 1 wherein the groove is provided from a distance D E of about 100 μm measured from circumference of the first wafer.
8. The method of claim 1 wherein the groove has straight sidewalls and resembling a rectangular shape.
9. The method of claim 1 wherein the groove has tapered sidewalls and resembling a reverse triangular shape.
10. The method of claim 1 further comprising forming a protective seal in close proximity with the groove, but closer to center of the wafer as compared with the groove.
11. A semiconductor device comprising:
a wafer with top and bottom surfaces, the wafer includes edge and non-edge regions;
a plurality of devices and partially processed TSV contacts disposed in the non-edge region;
a groove disposed at the edge region, wherein the groove enables edges of the wafer to be automatically trimmed off as the wafer is subjected to a back-grinding planarization process to expose the TSV contacts in the non-edge region of the wafer; and
a second wafer bonded to the wafer to form a device stack, wherein the second wafer is devoid of a groove at edge region of the second wafer.
12. The semiconductor device of claim 11 wherein the partially processed TSV contacts comprise a plurality of TSV holes which extend from the top surface and partially through the wafer and are filled with a conductive layer.
13. The semiconductor device of claim 11 wherein the groove comprises a depth D G of about 0.010 mm-0.5 mm and a width W G of about 0.010 mm-0.5 mm.
14. The semiconductor device of claim 11 wherein the groove is disposed from a distance D E of about 100 μm measured from circumference of the wafer.
15. The semiconductor device of claim 11 wherein the groove has straight sidewalls and resembles a rectangular shape.
16. The semiconductor device of claim 11 wherein the groove has tapered sidewalls and resembles a reverse triangular shape.
17. The semiconductor device of claim 11 wherein the groove comprises a ring structure.
18. The semiconductor device of claim 11 further comprising a protective seal in close proximity with the groove, but closer to center of the wafer as compared with the groove.
19. A method of forming a semiconductor device comprising:
providing first and second wafers with top and bottom surfaces, the first and second wafers include edge and non-edge regions, wherein the first and second wafers include devices formed in the non-edge region;
forming a groove at the edge region and partially processed TSV contacts at the non-edge region of the first and second wafers;
bonding the first and second wafers to form a device stack; and
subjecting the bottom surface of the first and second wafers to a back-grinding process, wherein the groove in the edge region of the first and second wafers enables edges of the first and second wafers to be automatically trimmed off as a back-grinding process exposes the TSV contacts in the non-edge region of the first and second wafers.
20. The method of claim 19 wherein the groove comprises a depth D G of about 0.010 mm-0.5 mm and a width W G of about 0.010 mm-0.5 mm.