LDMOS with two gate stacks having different work functions for improved breakdown voltage
View Patent ↗An LDMOS is formed with a second gate stack over the n − drift region, having a common gate electrode with the gate stack, and having a higher work function than the gate stack. Embodiments include forming a first conductivity type well, having a source, surrounded by a second conductivity type well, having a drain, in a substrate, forming first and second gate stacks on the substrate over a portion of the first well and a portion of the second well, respectively, the first and second gate stacks sharing a common gate electrode, and tuning the work functions of the first and second gate stacks to obtain a higher work function for the second gate stack. Other embodiments include forming the first gate stack with a first high-k dielectric and the second gate stack with a second high-k dielectric, and forming the first and second gate stacks with asymmetric dielectrics.
1. A method comprising:
forming a first well and a second well in a substrate, the second well surrounding the first well;
doping the first well with a first-type dopant and the second well with a second-type dopant;
forming a source in the first well and a drain in the second well;
forming a doped region of the first-type dopant in the first well, the doped region functioning as a body contact to the first well;
forming a first gate stack comprising HfSiON/La 2 O 3 on a portion of the first well;
forming a second gate stack comprising HfSiON/TiN/Al/TiN on a portion of the second well;
wherein the first and second gate stacks have a common gate electrode, and the second gate stack has a higher work function than the first gate stack.
2. The method according to claim 1 , comprising forming the first and second gate stacks by:
forming an oxide layer on the portion of the first well and on the portion of the second well;
removing the oxide layer from the portion of the first well, leaving the oxide layer on the portion of the second well;
forming a high-k dielectric layer on the oxide layer and on either the portion of the first well or on a second oxide layer thinner than the oxide layer over the portion of the first well; and
forming a common metal gate electrode on the high-k dielectric layer.
3. The method according to claim 2 , comprising forming the first and second gate stacks by:
forming a dummy gate electrode on the oxide layer prior to removing the oxide layer from the portion of the first well;
forming an interlayer dielectric over the entire substrate;
removing the dummy gate electrode, forming a cavity;
removing the oxide layer from the portion of the first well, leaving the oxide layer on the portion of the second well;
forming the high-k dielectric layer on the portion of the first well and on the oxide layer; and
forming the common metal gate electrode on the high-k dielectric layer.
4. The method according to claim 1 , comprising forming the first and second gate stacks by:
forming a first high-k dielectric layer or an oxide layer and a first high-k dielectric layer on the portion of the first well;
forming a second high-k dielectric layer or an oxide layer and a second high-k dielectric layer on the portion of the second well; and
forming a common gate electrode on both the first and second high-k dielectric layers.
5. The method according to claim 1 , comprising forming the first and second gate stacks by:
forming a dielectric layer on the portion of the first well and on the portion of the second well;
implanting a first dopant in the dielectric layer on the portion of the first well; and
implanting a second dopant, different from the first dopant, in the dielectric layer on the portion of the second well; and
forming a common gate electrode on the dielectric layer.
6. The method according to claim 1 , comprising forming the first and second gate stacks by:
forming a dielectric layer on the portion of the first well and on the portion of the second well;
depositing a work function adjustment material on the dielectric layer on the portion of the first well or the portion of the second well; and
forming a common gate electrode on the dielectric layer.
7. The method according to claim 1 , comprising forming the first and second gate stacks by:
forming a dummy gate stack on the substrate over the portions of the first well and the second well;
forming an interlayer dielectric (ILD) over the entire substrate;
removing the dummy gate stack, forming a cavity;
forming a first dielectric layer or an oxide layer and a first dielectric layer in the cavity on the portion of the first well;
forming a second dielectric layer or an oxide layer and a second dielectric layer in the cavity on the portion of the second well; and
forming a common metal gate electrode on the first and second dielectric layers.
8. The method according to claim 1 , comprising forming the first and second gate stacks by:
forming a dummy gate stack on the substrate over the portions of the first well and the second well;
forming an interlayer dielectric (ILD) over the entire substrate;
removing the dummy gate stack, forming a cavity;
forming a dielectric layer in the cavity;
implanting a first dopant in the dielectric layer on the portion of the first well;
implanting a second dopant, different from the first dopant, in the dielectric layer on the portion of the second well; and
forming a common metal gate on the dielectric layer.
9. The method according to claim 1 , comprising forming the first and second gate stacks by:
forming a dummy gate stack on the substrate over the portions of the first well and the second well;
forming an interlayer dielectric (ILD) over the entire substrate;
removing the dummy gate stack, forming a cavity;
forming a dielectric layer or an oxide layer and a dielectric layer in the cavity;
depositing a work function adjustment material on the dielectric layer on the portion of the first well or the portion of the second well; and
forming a common metal gate on the dielectric layer and on the work function adjustment material.
10. A method comprising: forming a lateral diffused MOS (LDMOS) by:
forming a first well and a second well in a substrate, the second well surrounding the first well;
doping the first well with a p-type dopant and the second well with an n-type dopant;
forming a source in the first well and a drain in the second well; and
forming a p-doped region in the first well, the p-doped region functioning as a body contact to the first well;
forming a first gate stack comprising HfSiON/La 2 O 3 on the substrate over a portion of the first well;
forming a second gate stack comprising HfSiON/TiN/Al/TiN on the substrate over a portion of the second well, the first and second gate stacks having a common gate electrode, and the second gate stack having a higher work function than the first gate stack, wherein the first and second gate stacks include different gate dielectric layers or asymmetrical dielectric layers.
11. The method according to claim 10 , comprising forming different gate dielectric layers by different dielectric materials on the portions of the first and second wells, respectively, or by forming a common dielectric layer on the portions of the first and second wells and implanting different dopants in the dielectric layer on the portions of the first well and the second well, respectively.
12. The method according to claim 10 , comprising forming asymmetrical dielectric layers by:
forming an oxide layer on the portion of the first well and on the portion of the second well;
removing the oxide layer from the portion of the first well, leaving the oxide layer on the portion of the second well; and
forming a dielectric layer on the portion of the first well and on the oxide layer.