A fin type transistor includes a dielectric layer on a substrate surface which serves to isolate the gate of the transistor from the substrate. The dielectric layer includes a non-selectively etched surface to produce top portions of fin structures which have reduce height variations across the wafer. The fin type transistor may also include a counter doped region at least below the S/D regions to reduce parasitic capacitance to improve its performance.
1. A method for forming a device comprising:
providing a substrate prepared with a device region which includes a doped isolation well and a dielectric layer over the doped isolation well in the substrate, wherein the dielectric layer includes a second dielectric sub-layer over a first dielectric sub-layer, wherein
the dielectric sub-layers comprise materials which can be removed selectively to each other, and
the first dielectric sub-layer comprises silicon nitride and the second dielectric sub-layer comprises silicon oxide;
forming a fin structure in the dielectric layer after the doped isolation well is provided, wherein forming the fin structure comprises
forming an opening in the dielectric layer to expose a portion of the substrate,
forming an amorphous semiconductor layer over the substrate to fill the opening and cover the dielectric layer,
removing excess amorphous semiconductor layer over the dielectric layer and above the opening to form a planar top surface between the dielectric layer and the amorphous semiconductor layer in the opening, and
performing an anneal to recrystallize the amorphous semiconductor layer in the opening;
removing a portion of the dielectric layer, wherein removing the portion of the dielectric layer leaves an upper portion of the fin structure extending above a top surface of the first dielectric sub-layer;
forming a gate which traverses the fin structure; and
forming doped S/D regions in the fin structure adjacent to the gate.
2. The method of claim 1 wherein the thickness of the first dielectric sub-layer is H 1 and the thickness of the second dielectric sub-layer is H 2 , wherein H 2 determines the height of a device in the device region.
3. The method of claim 1 wherein the anneal is performed prior to removing the excess amorphous semiconductor layer.
4. The method of claim 3 wherein the amorphous semiconductor layer comprises amorphous silicon layer.
5. The method of claim 4 wherein performing the anneal comprises annealing the amorphous silicon layer to form a crystalline silicon layer.
6. The method of claim 5 wherein the anneal is performed at a temperature of 600-800° C. for about 10-30 minutes.
7. The method of claim 6 wherein the fin structure includes a first portion and a second portion over the first portion.
8. The method of claim 7 wherein the first portion of the fin structure includes upper and lower first portions.
9. The method of claim 8 wherein:
the lower first portion of the fin structure includes the epitaxial layer, and
the upper first portion and second portion include epitaxial crystalline material, recrystallized crystalline material or a combination thereof.
10. The method of claim 9 further comprises doping the epitaxial layer with first polarity type dopants to form a counter doped region.
11. The method of claim 1 further comprises:
forming a counter doped region, and
wherein the counter doped region and S/D regions include first polarity type dopants and the doped isolation well includes a second polarity type dopants.
12. The method of claim 11 wherein the counter doped region is disposed in an upper portion of the doped isolation well.
13. The method of claim 12 wherein:
the counter doped well is disposed below the fin structure including the S/D regions and a channel between the S/D regions, or
the counter doped well is disposed below the fin structure including the S/D regions but not a channel between the S/D regions.
14. The method of claim 11 wherein the fin structure includes a first portion and a second portion over the first portion.
15. The method of claim 14 wherein the first portion of the fin structure serves as a depletion region separating the counter doped region and S/D regions.
16. A method of forming a device comprising:
providing a substrate prepared with a device region which includes a doped isolation well and a dielectric layer over the doped isolation well in the substrate, wherein the dielectric layer includes a second dielectric sub-layer over a first dielectric sub-layer, wherein
the dielectric sub-layers comprise materials which can be removed selectively to each other, and
the first dielectric sub-layer comprises silicon nitride and the second dielectric sub-laver comprises silicon oxide;
forming a fin structure after the doped isolation well is provided in an opening in the dielectric layer, wherein forming the fin structure comprises
forming an amorphous semiconductor layer over the substrate to fill the opening and cover the dielectric layer,
removing excess amorphous semiconductor layer over the dielectric layer and above the opening to form a planar top surface between the dielectric layer and the amorphous semiconductor layer in the opening, and
performing an anneal to recrystallize the amorphous semiconductor layer in the opening;
removing the second dielectric sub-layer selective to the first dielectric sub-layer to leave a portion of the fin structure extending above a top surface of the first dielectric sub-layer;
forming a gate which traverses the fin structure; and
forming doped S/D regions in the fin structure adjacent to the gate.
17. The method of claim 16 comprises forming a dielectric hard mask on an upper portion of the fin structure.