Scheme for planarizing through-silicon vias
View Patent ↗Generally, the subject matter disclosed herein relates to conductive via elements, such as through-silicon vias (TSV's), and methods for forming the same. One illustrative method disclosed herein includes forming a layer of isolation material above a via opening formed in a semiconductor device, the via opening extending into a substrate of the semiconductor device. The method also includes performing a first planarization process to remove at least an upper portion of the layer of isolation material formed outside of the via opening, and forming a conductive via element inside of the via opening after performing the first planarization process.
1. A method, comprising:
forming a layer of isolation material above a via opening formed in a semiconductor device, said via opening extending into a substrate of said semiconductor device;
performing a first planarization process to remove at least an upper portion of said layer of isolation material formed outside of said via opening; and
after performing said first planarization process, forming a layer of conductive material above said substrate to cover at least a remaining portion of said isolation layer, and thereafter forming a conductive via element inside of said via opening from said layer of conductive material.
2. The method of claim 1 , wherein performing said first planarization process comprises performing a chemical-mechanical polishing process.
3. The method of claim 2 , further comprising performing a cleaning process prior to forming said conductive via element, wherein said cleaning process is adapted to remove particles created during said first planarization process.
4. The method of claim 1 , wherein forming said layer of isolation material comprises forming said layer of isolation material above a bottom surface of said via opening, adjacent to sidewall surfaces of said via opening, and above an upper surface of an interlayer dielectric layer formed above said substrate.
5. The method of claim 1 , wherein forming said layer of isolation material comprises depositing a dielectric material layer comprising silicon dioxide.
6. The method of claim 1 , wherein forming said conductive via element comprises performing a second planarization process to remove at least a portion of said layer of conductive material formed outside of said via opening.
7. The method of claim 6 , wherein performing said second planarization process comprises performing a chemical-mechanical polishing process.
8. The method of claim 1 , wherein forming said layer of conductive material comprises performing an electrochemical deposition process to deposit a metal layer comprising copper.
9. The method of claim 1 , further comprising forming a barrier layer to cover at least said layer of isolation material prior to forming said conductive via element.
10. The method of claim 9 , further comprising forming said barrier layer after performing said first planarization process.
11. The method of claim 9 , wherein forming said barrier layer comprises depositing a conductive material comprising at least one of tantalum, tantalum nitride, titanium and titanium nitride.
12. A method, comprising:
forming a hardmask layer above a contact structure layer formed above a device layer of a substrate;
forming an opening that extends through said hardmask layer, said contact structure layer and said device layer, and into said substrate;
forming a layer of isolation material inside of said opening and above said hardmask layer;
performing a first chemical-mechanical polishing process to remove at least an upper portion of said layer of isolation material formed above said hardmask layer; and
after performing said first chemical-mechanical polishing process, forming a layer of conductive contact material to fill said opening.
13. The method of claim 12 , further comprising performing a cleaning process prior to forming said layer of conductive contact material, wherein said cleaning process is adapted to remove particles created during said first chemical-mechanical polishing process.
14. The method of claim 12 , further comprising performing a second chemical-mechanical polishing process after forming said layer of conductive contact material to expose said hardmask layer.
15. The method of claim 12 , wherein forming said layer of isolation material comprises forming a dielectric material layer comprising silicon dioxide.
16. The method of claim 12 , wherein forming said layer of conductive contact material comprises performing an electrochemical deposition process to form a metal layer comprising copper.
17. The method of claim 12 , further comprising forming a conductive barrier layer above said layer of isolation material prior to forming said layer of conductive contact material.
18. The method of claim 17 , wherein forming said conductive barrier layer comprises depositing a material layer comprising at least one of tantalum, tantalum nitride, titanium and titanium nitride.
19. The method of claim 12 , wherein performing said first chemical-mechanical polishing process comprises exposing said hardmask layer.
20. The method of claim 14 , further comprising forming one or more metallization layers above said contact structure layer after performing said second chemical-mechanical polishing process.
21. The method of claim 20 , further comprising forming an etch stop layer above said device layer prior to forming said one or more metallization layers.
22. The method of claim 12 , wherein forming said layer of isolation material comprises forming said layer of isolation material having at least a first thickness inside of said opening and at least a second thickness different than said first thickness above said hardmask layer.
23. The method of claim 22 , wherein said second thickness is at least two times greater than said first thickness.
24. The method of claim 22 , wherein said second thickness is at least four times greater than said first thickness.