Semiconductor system using germanium condensation
View Patent ↗A semiconductor method includes providing a silicon semiconductor substrate. A gate and a plurality of source/drain regions are formed on the silicon semiconductor substrate to form at least one pFET. A silicon-germanium layer is formed over the plurality of source/drain regions. The germanium is condensed from the silicon-germanium layer to form a plurality of source/drains in the plurality of source/drain regions by forming an oxide layer over the silicon-germanium layer. An interlevel dielectric layer is formed over the gate and the source/drain regions. A plurality of contacts is formed in the interlevel dielectric layer to the gate and the plurality of source/drain regions.
1. A semiconductor method comprising:
providing a substrate;
forming a gate and a plurality of source/drain regions on the substrate to form at least one pFET;
forming a silicon-germanium layer over the plurality of source/drain regions;
condensing the germanium from the silicon-germanium layer to form a plurality of source/drains in the plurality of source/drain regions by forming an oxide layer over the silicon-germanium layer; and
controlling silicon-germanium inter-diffusion into the source/drain regions with the thickness of the silicon-germanium layer and the thickness of the substrate.
2. The semiconductor method as claimed in claim 1 wherein:
forming a gate and a plurality of source/drain regions on the substrate to form at least one pFET also forms at least one nFET; and further comprising:
masking the nFET prior to forming a silicon-germanium layer over the source/drain regions of the pFET.
3. The semiconductor method as claimed in claim 1 , wherein:
condensing the germanium from the silicon-germanium layer uses an oxidation process.
4. The semiconductor method as claimed in claim 1 wherein:
condensing the germanium from the silicon-germanium layer forms a germanium-rich layer over the plurality of source/drain regions; and further comprising:
driving the germanium into the plurality of source/drain regions.
5. The semiconductor method as claimed in claim 1 , wherein:
condensing the germanium from the silicon-germanium layer to form a plurality of source/drains in the plurality of source/drain regions further comprises an annealing process.
6. The semiconductor method as claimed in claim 1 , further comprising:
forming an insulating spacer around the gate.
7. A semiconductor method system comprising:
providing a silicon semiconductor substrate;
forming a plurality of n-wells in the silicon semiconductor substrate;
forming a plurality of p-wells in the silicon semiconductor substrate;
forming a plurality of gates and a plurality of source/drain regions adjacent the gates over the plurality of n-wells to form a plurality of pFETs and over the plurality of p-wells to form a plurality of nFETs;
masking the plurality of nFETs;
forming a silicon-germanium layer over the plurality of source/drain regions of the plurality of pFETs;
condensing the germanium from the silicon-germanium layer to form a plurality of source/drains in the plurality of source/drain regions of the plurality of pFETs by forming an oxide layer over the silicon-germanium layer;
controlling silicon-germanium inter-diffusion into the source/drain regions with the thickness of the silicon-germanium layer and the thickness of the silicon semiconductor substrate;
forming an interlevel dielectric layer over the plurality of gates and the plurality of source/drain regions; and
forming a plurality of contacts in the interlevel dielectric layer to the plurality of gates and the plurality of source/drain regions.
8. The semiconductor method as claimed in claim 7 , wherein:
condensing the germanium from the silicon-germanium layer uses an oxidation process.
9. The semiconductor method as claimed in claim 7 wherein:
condensing the germanium from the silicon-germanium layer forms a germanium-rich layer over the plurality of source/drain regions of the plurality of pFETs; and further comprising:
driving the germanium into the plurality of source/drain regions of the plurality of pFETs.
10. The semiconductor method as claimed in claim 7 , wherein:
condensing the germanium from the silicon-germanium layer to form a plurality of source/drains in the plurality of source/drain regions of the plurality of pFETs further comprises an annealing process.
11. The semiconductor method as claimed in claim 7 wherein:
providing the silicon semiconductor substrate provides at least one of a silicon substrate, a semiconductor-on-insulator substrate, and combinations thereof.
12. The semiconductor method as claimed in claim 7 , further comprising:
forming an insulating spacer around the plurality of gates.
13. A method comprising:
providing a substrate;
forming a gate and a plurality of source/drain regions on the substrate to form at least one pFET;
forming a layer including a strain inducing element over the plurality of source/drain regions;
condensing a strain inducing element from the layer including a strain inducing element to form a plurality of source/drains in the plurality of source/drain regions by forming an oxide layer over the layer including a strain inducing element; and
controlling diffusion of the strain inducing element into the source/drain regions with the thickness of the layer including a strain inducing element and the thickness of the substrate.