Driver-based distributed multi-path ESD scheme

1. A circuit comprising:

an ESD trigger circuit; and

a plurality of I/O cells, each of the I/O cells including a first driver having a first source, a first drain, and a first gate, and a second driver having a second source, a second drain, and a second gate, wherein the ESD trigger circuit provides a first signal using a first ESD trigger terminal of the ESD trigger circuit to turn on the first driver in each of the I/O cells during an ESD event and a second signal using a second ESD trigger terminal of the ESD trigger circuit to turn on the second driver in each of the I/O cells during the ESD event to form a plurality of parallel ESD paths that include turned-on first drivers and turned-on second drivers;

wherein each of the I/O cells further includes:

an I/O pad coupled to the first and second drains; and

a compare circuit coupled to the I/O pad, wherein the compare circuit receives the first and second signals, and compares a pad voltage at the I/O pad with the first and second signals.

2. The circuit according to claim 1 , wherein each of the I/O cells further includes:

a first pass-gate circuit having a first NMOS gate, a first PMOS gate, a first input, and a first output; and

a second pass-gate circuit having a second NMOS gate, a second PMOS gate, a second input, and a second output, wherein the first output is coupled to the first gate and the second output is coupled to the second gate, the first and second pass-gates are turned off during the ESD event, and the first and second pass-gates are turned on during normal operations.

3. The circuit according to claim 2 , wherein each of the I/O cells further includes:

a first transistor having a third source, a third drain, and a third gate; and

a second transistor having a fourth source, a fourth drain, and a fourth gate, wherein the first signal is received at the third gate, the first PMOS gate, and the second PMOS gate, and the second signal is received at the fourth gate, the first NMOS gate, and the second NMOS gate.

4. The circuit according to claim 3 , wherein the third drain is coupled to the first gate, and the fourth drain is coupled to the second gate.

5. The circuit according to claim 1 , wherein the compare circuit provides a third signal to turn off the first driver and a fourth signal to turn off the second driver when the pad voltage is higher than the first and second signals.

6. The circuit according to claim 1 , wherein the compare circuit is coupled to the first and second gates.

7. The circuit according to claim 1 , wherein ESD current is distributed through the first driver of each of the I/O cells during the ESD event.

8. A method comprising:

providing a plurality of I/O cells, wherein each of the I/O cells includes a first driver having a first source, a first drain, and a first gate and a second driver having a second source, a second drain and a second gate; and

providing a first signal using a first ESD trigger terminal of an ESD trigger circuit to turn on the first driver in each of the I/O cells during an ESD event and a second signal using a second ESD trigger terminal of the ESD trigger circuit to turn on the second driver in each of the I/O cells during the ESD event to form a plurality of parallel ESD paths that include turned-on first drivers and turned-on second drivers;

wherein each of the I/O cells further includes:

an I/O pad coupled to the first and second drains; and

a compare circuit coupled to the I/O pad, the method further comprising:

receiving, at the compare circuit, the first and second signals; and

comparing a pad voltage at the I/O pad with the first and second signals.

9. The method according to claim 8 , wherein each of the I/O cells further includes:

a first pass-gate circuit having a first NMOS gate, a first PMOS gate, a first input, and a first output; and

a second pass-gate circuit having a second NMOS gate, a second PMOS gate, a second input, and a second output, the method further comprising:

coupling the first output to the first gate and the second output to the second gate;

turning off the first and second pass-gates during the ESD event; and

turning on the first and second pass-gates during normal operations.

10. The method according to claim 9 , wherein each of the I/O cells further includes:

a first transistor having a third source, a third drain, and a third gate; and

a second transistor having a fourth source, a fourth drain, and a fourth gate, the method further comprising:

receiving the first signal at the third gate, the first PMOS gate, and the second PMOS gate; and

receiving the second signal at the fourth gate, the first NMOS gate, and the second NMOS gate.

11. The method according to claim 10 , further comprising coupling the third drain to the first gate, and the fourth drain to the second gate.

12. The method according to claim 8 , further comprising providing, via the compare circuit, a third signal to turn off the first driver and a fourth signal to turn off the second driver when the pad voltage is higher than the first and second signals.

13. The method according to claim 8 , further comprising coupling the compare circuit to the first and second gates.

14. A ring I/O circuit comprising:

an ESD trigger circuit having a first ESD trigger terminal and a second ESD trigger terminal; and

a plurality of I/O cells, each of the I/O cells including:

a first driver having a first source, a first drain, and a first gate;

a second driver having a second source, a second drain, and a second gate,

wherein first and second signals are respectively provided using the first and second ESD trigger terminals to turn on the first and second drivers in each of the I/O cells during an ESD event to form a plurality of parallel ESD paths that include turned-on first and second drivers; wherein each of the I/O cells further includes:

an I/O pad coupled to the first and second drains; and

a compare circuit coupled to the I/O pad, the first gate, and the second gate,

wherein the compare circuit receives the first and second signals, and compares a pad voltage at the I/O pad with the first and second signals, and

wherein the compare circuit provides a third signal to turn off the first driver and a fourth signal to turn off the second driver when the pad voltage is higher than the first and second signals.

15. The ring I/O circuit according to claim 14 , wherein each of the I/O cells further includes:

a first pass-gate circuit having a first NMOS gate, a first PMOS gate, a first input, and a first output;

a second pass-gate circuit having a second NMOS gate, a second PMOS gate, a second input, and a second output;

a first transistor having a third source, a third drain, and a third gate; and

a second transistor having a fourth source, a fourth drain, and a fourth gate,

wherein the first output is coupled to the first gate, the second output is coupled to the second gate, the third drain is coupled to the first gate, and the fourth drain is coupled to the second gate,

wherein the first signal is received at the third gate, the first PMOS gate, and the second PMOS gate, and the second signal is received at the fourth gate, the first NMOS gate, and the second NMOS gate, and

wherein the first and second pass-gates are turned off during the ESD event, and the first and second pass-gates are turned on during normal operations.