A method of forming a device is disclosed. The method includes providing a substrate prepared with a cell area separated by other active areas by isolation regions. First and second gates of first and second transistors in the cell area are formed. The first gate includes first and second sub-gates separated by a first intergate dielectric layer. The second gate includes a second sub-gate surrounding a first sub-gate. The first and second sub-gates of the second gate are separated by a second intergate dielectric layer. First and second junctions of the first and second transistors are formed. The method also includes forming a first gate terminal coupled to the second sub-gate of the first transistor and a second gate terminal coupled to at least the first sub-gate of the second transistor.
1. A method of forming a device comprising:
providing a substrate prepared with a cell area separated by other active areas by isolation regions;
forming first and second gates of first and second transistors in the cell area, wherein
the first gate includes first and second sub-gates separated by a first intergate dielectric layer, and
the second gate includes a second sub-gate surrounding a first sub-gate, the first and second sub-gates of the second gate are separated by a second intergate dielectric layer;
forming first and second junctions of the first and second transistors;
forming a first gate terminal coupled to the second sub-gate of the first transistor; and
forming a second gate terminal coupled to at least the first sub-gate of the second transistor.
2. The method of claim 1 comprises:
forming a first cell terminal coupled to the first junction of the first transistor; and
forming a second cell terminal coupled to the first junction of the second transistor.
3. The method of claim 2 wherein:
the first transistor serves as a control gate;
the second transistor serves as a select gate;
the second cell terminal serves as a bitline; and
the second gate terminal serves as a wordline.
4. The method of claim 1 wherein forming the second junctions of the first and second transistors comprises forming a common second junction of the first and second transistors.
5. The method of claim 1 wherein:
the first transistor serves as a control gate;
the second transistor serves as a select gate;
a second cell terminal coupled to the second transistor serves as a bitline; and
the second gate terminal serves as a wordline.
6. The method of claim 1 wherein forming the first and second gates comprises:
forming a first sub-gate layer on the substrate;
patterning the first sub-gate layer to form first sub-gates of the first and second gates;
forming a common intergate dielectric layer on the substrate covering the first sub-gates, the common intergate dielectric layer serves as the first and second intergate dielectric layers of the first and second gates;
forming a second sub-gate layer on the substrate over the common intergate dielectric layer; and
patterning the second sub-gate layer to form first and second gates, wherein the second sub-gates of the first and second gates wrap around the first sub-gates of the first and second gates.
7. The method of claim 6 wherein:
the first and second junctions of the first and second transistors include a heavily doped portion and a lightly doped extension portion extending from the first gate to the second gate; and
comprises
forming the lightly doped extension portion of the first and second junctions after forming the first sub-gates of the first and second gates, and
forming the heavily doped portion of the first and second junctions after forming the second sub-gates of the first and second gates.
8. The method of claim 7 wherein the second sub-gate surrounding the first sub-gate of the second gate increases the distance from an edge of the first sub-gate to the heavily doped portion of the first junction to reduce junction leakage.
9. The method of claim 6 wherein patterning the second sub-gate layer also forms gates of other transistors in the device.
10. The method of claim 1 comprises forming a gate dielectric layer on the substrate prior to forming the first sub-gate layer, wherein the gate dielectric layer includes a tunneling window under the first sub-gate of the first gate.
11. The method of claim 10 wherein forming the gate dielectric layer comprises:
forming a first gate dielectric layer on the substrate;
patterning the first gate dielectric layer to form an opening corresponding to the tunneling window; and
forming a second gate dielectric layer over the first gate dielectric layer and covering the opening to form the tunneling window.
12. The method of claim 11 wherein the second gate dielectric layer also serves as gate dielectric layer of other transistors in the device.
13. The method of claim 1 wherein the intergate dielectric layer comprises an oxide-nitride-oxide stack.
14. The method of claim 1 wherein the first intergate dielectric layer comprises multiple dielectric layers.
15. The method of claim 1 wherein the second gate terminal is coupled to the first and second sub-gates of the second gate.
16. The method of claim 1 wherein the second gate terminal is coupled to the first sub-gate of the second gate while the second sub-gate of the second gate is floated.
17. A method of forming a device comprising:
providing a substrate prepared with a cell area;
forming first and second gates of first and second transistors in the cell area, wherein
the first gate includes first and second sub-gates separated by a first intergate dielectric layer, and
the second gate includes a second sub-gate surrounding a first sub-gate, the first and second sub-gates of the second gate are separated by a second intergate dielectric layer;
forming first and second junctions of the first and second transistors;
forming a first gate terminal coupled to the second sub-gate of the first transistor; and
forming a second gate terminal coupled to at least the first sub-gate of the second transistor.
18. The method of claim 17 wherein the second sub-gate surrounding the first sub-gate of the second gate increases the distance from an edge of the first sub-gate to the heavily doped portion of the first junction to reduce junction leakage.
19. The method of claim 17 wherein:
the first and second junctions of the first and second transistors include a heavily doped portion and a lightly doped extension portion extending from the first gate to the second gate.
20. The method of claim 19 comprises:
forming the lightly doped extension portion of the first and second junctions after forming the first sub-gates of the first and second gates, and
forming the heavily doped portion of the first and second junctions after forming the second sub-gates of the first and second gates.
21. The method of claim 20 comprises:
forming first and second buried doped regions adjacent to the first gate of the first transistor.
22. The method of claim 21 wherein the buried doped regions overlap the heavily doped portion and the lightly doped extension portion of the first gate and extend beneath the first gate.
23. The method of claim 17 wherein forming the second junctions of the first and second transistors comprises forming a common second junction of the first and second transistors.
24. The method of claim 17 wherein forming the first and second gates comprises:
forming a first sub-gate layer on the substrate;
patterning the first sub-gate layer to form first sub-gates of the first and second gates;
forming a common intergate dielectric layer on the substrate covering the first sub-gates, the common intergate dielectric layer serves as the first and second intergate dielectric layers of the first and second gates;
forming a second sub-gate layer on the substrate over the common intergate dielectric layer; and
patterning the second sub-gate layer to form first and second gates, wherein the second sub-gates of the first and second gates wrap around the first sub-gates of the first and second gates.
25. The method of claim 17 comprises forming a gate dielectric layer on the substrate prior to forming the first sub-gate layer, wherein the gate dielectric layer includes a tunneling window under the first sub-gate of the first gate.