Integrated circuits including a dummy metal feature and methods of forming the same
Integrated circuits and methods of forming the same are provided herein. In an embodiment, an integrated circuit includes a semiconductor substrate that has an isolated well. A multilayer metallization stack overlies the semiconductor substrate. The multilayer metallization stack includes a metal layer, a functional via, and a dummy metal feature. The metal layer includes a first line in electrical communication with the isolated well through a contact. The functional via is in electrical communication with the first line and the contact. The dummy metal feature is in electrical communication with the functional via.
1. An integrated circuit comprising:
a semiconductor substrate comprising an isolated well;
a multilayer metallization stack overlying the semiconductor substrate, wherein the multilayer metallization stack comprises:
a metal layer comprising a first line in electrical communication with the isolated well through a contact;
a functional via in electrical communication with the first line and the contact, and
a dummy metal feature in electrical communication with the functional via, wherein the dummy metal feature comprises a plurality of non-connecting vias in electrical communication with the first line and the functional via.
2. The integrated circuit of claim 1 , wherein the functional via is disposed in series between the first line and another line of another metal layer of the integrated circuit.
3. The integrated circuit of claim 1 , wherein the dummy metal feature is an open metal feature.
4. The integrated circuit of claim 1 , wherein the dummy metal feature is chosen from a non-connecting via, a sacrificial portion of the first line, or a combination thereof.
5. The integrated circuit of claim 1 , wherein the plurality of non-connecting vias is arranged in an array at an expanded portion of the first line.
6. The integrated circuit of claim 1 , wherein at least one intervening metal layer is disposed between the metal layer and the semiconductor substrate.
7. The integrated circuit of claim 1 , further comprising a non-volatile memory device disposed in and on the isolated well.
8. The integrated circuit of claim 1 , free of a diode in direct electrical communication with the isolated well.
9. The integrated circuit of claim 1 , wherein the isolated well is an isolated p-well.
10. The integrated circuit of claim 9 , wherein the isolated p-well is isolated by n-doped regions immediately adjacent the isolated p-well in the semiconductor substrate.
11. The integrated circuit of claim 10 , wherein the isolated p-well is further isolated by a deep n-well underlying the isolated p-well.
12. The integrated circuit of claim 10 , further comprising a body contact in electrical communication with one or more of the n-doped regions immediately adjacent the isolated p-well.
13. The integrated circuit of claim 12 , wherein the metal layer further comprises a second line in electrical communication with the body contact, wherein the first line and the second line are isolated from direct electrical communication by adjacent portions of interlayer dielectric layers.
14. An integrated circuit comprising:
a semiconductor substrate comprising an isolated well;
a multilayer metallization stack overlying the semiconductor substrate, wherein the multilayer metallization stack comprises:
a metal layer comprising a first line in electrical communication with the isolated well through a contact;
a functional via in electrical communication with the first line and the contact, and
a dummy metal feature in electrical communication with the functional via, wherein the dummy metal feature comprises an expanded portion of the first line as a sacrificial portion of the first line, and wherein the expanded portion is in electrical communication with the functional via through a branched portion of the first line.
15. An integrated circuit comprising:
a semiconductor substrate comprising an isolated p-well, wherein the isolated p-well is isolated by n-doped regions immediately adjacent the isolated p-well in the semiconductor substrate and by a deep n-well underlying the isolated p-well;
a body contact in electrical communication with one or more of the n-doped regions immediately adjacent the isolated p-well;
a non-volatile memory device disposed in and on the isolated p-well;
a multilayer metallization stack overlying the semiconductor substrate, wherein the multilayer metallization stack comprises:
a metal layer comprising:
a first line in electrical communication with the isolated p-well through a contact; and
a second line in electrical communication with the body contact, wherein the first line and the second line are isolated from direct electrical communication by adjacent portions of interlayer dielectric layers;
a functional via in electrical communication with the first line and the contact; and
a dummy metal feature in electrical communication with the functional via, wherein the dummy metal feature comprises a plurality of non-connecting vias in electrical communication with the first line and the functional via.
16. The integrated circuit of claim 15 , free of a diode in direct electrical communication with the isolated p-well.