Methods of forming replacement gate structures for semiconductor devices and the resulting semiconductor products
View Patent ↗One method disclosed includes, forming a sacrificial gate structure trench in a stack of sacrificial material layers, forming a sacrificial gate structure within the trench, performing at least one process operation to remove at least portions of the stack of sacrificial material layers and thereby expose sidewalls of the sacrificial gate structure, forming a sidewall spacer adjacent the exposed sidewalls of the sacrificial gate structure, removing the sacrificial gate structure so as to define a replacement gate cavity between the spacers, forming a replacement gate structure in the replacement gate cavity, and forming a gate cap above the replacement gate structure within the replacement gate cavity.
1. A method of forming a replacement gate structure for a device, comprising:
forming a stack of sacrificial material layers above a semiconductor substrate;
forming at least a sacrificial gate structure trench in said stack of sacrificial material layers;
forming a sacrificial gate structure within said sacrificial gate structure trench;
performing at least one process operation to remove at least portions of said stack of sacrificial material layers and thereby expose sidewalls of said sacrificial gate structure;
forming a sidewall spacer adjacent at least said exposed sidewalls of said sacrificial gate structure;
removing at least said sacrificial gate structure so as to define a replacement gate cavity between said sidewall spacers;
forming a replacement gate structure in said replacement gate cavity; and
forming a gate cap above said replacement gate structure within said replacement gate cavity.
2. The method of claim 1 , wherein said device is one of a FinFET device or a planar transistor device.
3. The method of claim 1 , wherein forming said stack of sacrificial material layers above said semiconductor substrate comprises:
forming a first layer of silicon dioxide on said semiconductor substrate;
forming a second layer of polysilicon or amorphous silicon on said first layer; and
forming a layer of silicon nitride on said second layer.
4. The method of claim 1 , wherein forming said stack of sacrificial material layers above said semiconductor substrate comprises:
forming a first layer of high-k insulation material on said semiconductor substrate;
forming a second layer of silicon dioxide on said first layer; and
forming a layer of silicon nitride on said second layer.
5. The method of claim 1 , wherein forming said sacrificial gate structure within said sacrificial gate structure trench comprises performing a deposition process to form a sacrificial gate insulation layer within said sacrificial gate structure trench.
6. The method of claim 1 , wherein forming said sacrificial gate structure within said sacrificial gate structure trench comprises performing a thermal growth process to form a thermally grown sacrificial gate insulation layer within said sacrificial gate structure trench.
7. The method of claim 1 , wherein, after forming said sidewall spacer, removing any remaining exposed portions of said stack of sacrificial material layers.
8. A method of forming a replacement gate structure for a device, comprising:
forming a stack of sacrificial material layers above a semiconductor substrate;
performing at least one first etching process on said stack of sacrificial material layers to define a sacrificial gate structure trench in said stack of sacrificial material layers;
forming a sacrificial gate structure within said sacrificial gate structure trench;
forming a first gate cap above said sacrificial gate structure within said sacrificial gate structure trench;
after forming said first gate cap, performing at least one process operation to remove at least portions of said stack of sacrificial material layers and thereby expose sidewalls of said sacrificial gate structure;
forming a sidewall spacer adjacent at least said exposed sidewalls of said sacrificial gate structure;
forming a layer of insulating material adjacent said sidewall spacers;
after forming said layer of insulating material, removing said first gate cap and said sacrificial gate structure so as to define a replacement gate cavity;
forming a replacement gate structure in said replacement gate cavity; and
forming a second gate cap above said replacement gate structure within said replacement gate cavity.
9. The method of claim 8 , wherein forming said stack of sacrificial material layers above said semiconductor substrate comprises:
forming a first layer of silicon dioxide on said semiconductor substrate;
forming a second layer of polysilicon or amorphous silicon on said first layer; and
forming a layer of silicon nitride on said second layer.
10. The method of claim 8 , wherein forming said stack of sacrificial material layers above said semiconductor substrate comprises:
forming a first layer of high-k insulation material on said semiconductor substrate;
forming a second layer of silicon dioxide on said first layer; and
forming a layer of silicon nitride on said second layer.
11. The method of claim 8 , wherein forming said sacrificial gate structure within said sacrificial gate structure trench comprises performing a deposition process to form a sacrificial gate insulation layer within said sacrificial gate structure trench.
12. The method of claim 8 , wherein forming said sacrificial gate structure within said sacrificial gate structure trench comprises performing a thermal growth process to form a thermally grown sacrificial gate insulation layer within said sacrificial gate structure trench.
13. The method of claim 8 , wherein, after forming said sidewall spacer, removing any remaining exposed portions of said stack of sacrificial material layers.
14. A method of forming a FinFET device, comprising:
forming a plurality of trenches in a semiconductor substrate to define at least one fin;
forming a layer of insulating material in said plurality of trenches, said layer of insulating material having an initial upper surface that exposes a first height of said fin;
forming a plurality of sacrificial materials around said fin and above said layer of insulating material;
performing at least one etching process on said plurality of sacrificial materials to define a sacrificial gate structure trench in said plurality of sacrificial materials in an area corresponding to a channel region of said device, said sacrificial gate structure trench exposing an upper surface of said layer of insulating material; and
performing an etching process through said sacrificial gate structure trench to reduce a thickness of said exposed portion of said layer of insulating material such that, after performing said etching process, said exposed portion of said layer of insulating material has an etched upper surface that is at a level that is below said initial upper surface and exposes a second height of said fin under said sacrificial gate structure trench, wherein said second height is greater than said first height.
15. The method of claim 14 , further comprising:
forming a sacrificial gate structure in said sacrificial gate structure trench;
removing said sacrificial gate structure to define a replacement gate cavity positioned between two sidewall spacers; and
forming a replacement gate structure in said replacement gate cavity above said etched upper surface of said layer of insulating material and around said fin having said second height.