Magnetic memory with tunneling magnetoresistance enhanced spacer layer

1. A method of forming a device comprising:

providing a substrate comprising circuit component formed on a substrate surface;

performing back end of line processing to form an upper inter level dielectric (ILD) layer over the substrate, wherein the upper ILD layer comprises a plurality of ILD levels;

forming a magnetic tunneling junction (MTJ) stack in between adjacent ILD levels of the upper ILD layer, wherein the MTJ stack comprises

a free layer,

a tunneling barrier layer, and

a fixed layer, wherein the fixed layer comprises

a polarizer layer,

a composite texture breaking layer comprising an amorphous layer and a non-magnetic layer, the amorphous layer is disposed above the non-magnetic layer,

a synthetic antiferromagnetic (SAF) layer

wherein the composite texture breaking layer is disposed above the SAF layer, the polarizer layer is disposed above the composite texture breaking layer, the tunneling barrier layer is disposed above the polarizer layer and the free layer is disposed above the tunneling barrier layer, and

wherein the composite texture breaking layer breaks a crystalline texture of the SAF layer.

2. The method of claim 1 wherein the SAF layer comprises a first magnetic layer, a second magnetic layer and a coupling layer, wherein the coupling layer is sandwiched between the first and second magnetic layers, and wherein the second magnetic layer is proximate to the texture breaking layer.

3. The method of claim 2 wherein:

the first magnetic layer comprises n multilayer of cobalt/platinum (Co/Pt), cobalt/palladium (Co/Pd) or cobalt/nickel (Co/Ni); and

the second magnetic layer comprises m multilayer of cobalt/platinum (Co/Pt), cobalt/palladium (Co/Pd) or cobalt/nickel (Co/Ni), and

wherein n is an integer larger than m.

4. The method of claim 2 wherein:

the first magnetic layer comprises a multilayer of cobalt/platinum (Co/Pt), cobalt/palladium (Co/Pd) or cobalt/nickel (Co/Ni); and

the second magnetic layer comprises a multilayer of cobalt/platinum/cobalt (Co/Pt/Co).

5. The method of claim 4 wherein a layer of Co/Pt/Co of the second magnetic layer comprises a platinum layer sandwiched between two cobalt layers, wherein the platinum layer is thicker than the cobalt layer.

6. The method of claim 3 wherein the non-magnetic layer comprises a ruthenium layer, and wherein the ruthenium layer is proximate to the SAF layer.

7. The method of claim 6 wherein the amorphous layer comprises a tantalum layer.

8. The method of claim 7 wherein the composite texture breaking layer further comprises a cobalt or cobalt iron (CoFe) alloy layer, and wherein the cobalt or CoFe alloy layer is sandwiched between the tantalum layer and ruthenium layer.

9. The method of claim 4 wherein the non-magnetic layer comprises a ruthenium layer, and wherein the ruthenium layer is proximate to the SAF layer.

10. The method of claim 9 wherein the amorphous layer comprises a tantalum layer.

11. The method of claim 10 wherein the composite texture breaking layer further comprises a cobalt or cobalt iron (CoFe) alloy layer, and wherein the cobalt or CoFe alloy layer is sandwiched between the tantalum layer and ruthenium layer.

12. The method of claim 1 wherein forming the MTJ stack in between adjacent ILD levels comprises:

forming an opening in a lower dielectric layer of a lower ILD level of the adjacent ILD levels;

forming a bottom electrode layer over the lower dielectric layer and fills the opening;

planarizing the bottom electrode layer to form bottom electrode in the opening and removing excess bottom electrode layer in areas other than the opening;

depositing remaining MTJ stack layers over the lower dielectric layer and the bottom electrode; and

patterning the remaining MTJ stack layers to form the MTJ stack and a top electrode of the MTJ stack over the bottom electrode.

13. The method of claim 12 where depositing the remaining MTJ stack layers comprises sequentially depositing the fixed layer, the tunneling barrier layer, the free layer and a top electrode layer over the lower dielectric layer and the bottom electrode.

14. The method of claim 13 comprising:

forming an intermediate dielectric layer over the lower dielectric layer and covers the patterned MTJ stack; and

performing a planarizing process to form planar top surface between top of the MTJ stack and the intermediate dielectric layer.

15. The method of claim 11 further comprising forming a metal line over the intermediate dielectric layer, wherein the metal line is coupled to the MTJ stack.

16. A device comprising:

a substrate comprising circuit component disposed over a substrate surface;

an upper inter level dielectric (ILD) layer disposed over the substrate, wherein the upper ILD layer comprises a plurality of ILD levels; and

a magnetic tunneling junction (MTJ) stack disposed in between adjacent ILD levels of the upper ILD layer, wherein the MTJ stack comprises

a free layer,

a tunneling barrier layer, and

a fixed layer, wherein the fixed layer comprises

a polarizer layer,

a composite texture breaking layer comprising an amorphous layer and a non-magnetic, the amorphous layer is disposed above the non-magnetic layer,

a synthetic antiferromagnetic (SAF) layer

wherein the composite texture breaking layer is disposed above the SAF layer, the polarizer layer is disposed above the composite texture breaking layer, the tunneling barrier layer is disposed above the polarizer layer and the free layer is disposed above the tunneling barrier layer, and

wherein the composite texture breaking layer breaks a crystalline texture of the SAF layer.

17. The device of claim 16 wherein the SAF layer comprises a first magnetic layer, a second magnetic layer and a coupling layer, wherein the coupling layer is sandwiched between the first and second magnetic layers.

18. The device of claim 17 wherein the composite texture breaking layer further comprises a cobalt or cobalt iron (CoFe) alloy layer.

19. The device of claim 18 wherein the non-magnetic layer comprises a ruthenium layer.

20. The device of claim 19 wherein the amorphous layer comprises a tantalum layer.